Success in the semiconductor industry depends on getting increasingly complex products to market on time. This industry has worked hard over the years to realize gains promised by Moore’s Law, and the companies that implement it have reliably delivered products with increased performance at decreased cost per function (CPF) to consumers. As a result, semiconductor device and product complexity have risen sharply and market demands have increased significantly. ASICs with 100 million gates are now commonplace and retail shelves are littered with ICs, each with design budgets measured in millions of dollars.
Consequently, design teams continue to face aggressive product life cycles that are historically the shortest of any industry.1 Requirements for the future seem clear: designers must deliver increasingly complex, low-CPF chips to market faster. Failure to increase performance (and therefore complexity) quickly enough means products will not be competitive. On the other hand, failure to get products to market on time means a loss of available revenue.
Designers will count on new silicon technology for performance gains. When it comes to taking advantage of new silicon technology, design enablement teams must deliver accurate process design kits (PDKs) to mitigate the complexity of evolving semiconductor processes. These kits must accurately model the process and performance of the completed device. They also must be available to designers on a schedule that supports time-to-market goals.
Enabling Product Delivery
One way to enable earlier product delivery with shorter design cycles is to provide PDKs to design teams earlier in the design cycle and improve the accuracy of those kits. Of course, one challenge with early kits is accuracy. Since the PDK essentially represents a contract between manufacturing and design, early delivery can be problematic. The availability of kits can impact design rework if they change after design work has begun (Fig. 1).
While it’s possible for designers to begin their work with “initial design kits,” any work done prior to the release of the “production design kit” is subject to potentially costly rework. Additionally, rushing kits to production can cause unplanned design kit revisions late in development. In either case, the resulting design rework and product delays translate to lost revenue. Late kits or problems with design kit accuracy impact time-to-market.
The primary reason for variability in design kit schedules is that process development usually is incomplete when kits are needed. Simply put, uncertainty in device performance and process parameters means model accuracy is a function of time.2Figure 2 illustrates the tradeoff between development uncertainty and design rework risk as a function of time. In general, uncertainty decreases with time, but new findings during development can cause temporary spikes in uncertainty. As previously discussed, from a design perspective, any kit inaccuracies that touch production design efforts can lead to design rework, which inevitably leads to time-to-market delays.
The Effect Of Context
Consider the effect of context on transistor performance. The sensitivity of transistors to nearby geometries has been increasing with each node. These variations are a function of physical design, which allows them to be modeled in design kits. Failure to model these effects accurately can result in timing closure problems on silicon, making kit accuracy critical. Figure 3 illustrates the effect of nearby wells on the drive current of standard core CMOS transistors node over node. Comprehensive equations are required to model the various interactions of the stronger context effects as dimensions scale down in future nodes.
However, these types of effects are large and can be difficult to model. Accurately representing them in the design kit requires careful evaluation of test silicon, which takes time. When process uncertainty is high (early in the development cycle), data demonstrating these effects used for modeling may be unreliable. Waiting for reliable data can delay design kits. Often, a decision must be made about how much risk is acceptable.
A Possible Solution: Target Kits
Traditionally, kits are viewed as an accurate representation of the actual process as measured in actual silicon. One possible solution to this problem of kit uncertainty is to simply eliminate it by turning the problem on its head. If the initial design kit is viewed as the authoritative target for the process and a commitment is made to move silicon performance toward that target, then design rework can be avoided. This “silicon closure” phase can run concurrently with new product design, reducing product cycle time and the risk of design rework (Fig. 4).
Effective use of “target kits” relies on accurate estimation of what silicon performance must be achieved when products are released into the marketplace. This can be challenging, since it requires competitive analysis, anticipating both physics and process performance as well as future production costs. Fundamentally, this approach accepts the risks associated with those predictions and places the responsibility of managing them on the silicon closure activity.
Obviously, if performance targets are too aggressive, closure might not be possible. Similarly, weak targets for the technology can result in products that are unable to compete in the marketplace at the time of production. As with any effective business process, continuous benchmarking evaluation and management review of silicon development progress is useful in mitigating this risk during development. When possible, these reviews should include both design and process team management.
The approach of using target kits can be leveraged to manage time-to-market risk by both increasing the predictability of the design process and by allowing silicon process development to run concurrently with initial design work. While the approach itself is not without risk, the result of increased design schedule predictability can pay off in increasingly competitive markets.
- B. Prasad, V5N4, Pricing Strat Prac, p. 132, 1997
- Mansfield, et al.,Proceedings of SPIE Vol. 6156, 2006