Electronic Design

Process Migration For IP And ASICs

Upon completion of an ASIC design, unexpected results often appear because they weren't predicted accurately by the design tools. For instance, the chip size may be too large, the circuit may not clock fast enough, or it may consume too much power. Rather than redesign the chip, another option might be to use automatic process migration. This design-automation methodology takes a finished physical layout and automatically converts it to another set of process design rules, enabling it to be fabricated in a new target process technology.

Process migration can be used to migrate a design to the next technology node, enabling higher integration, smaller die size, higher performance, and better power consumption. It also can be used to migrate a design to a different fabrication facility or foundry within the same technology node, mainly for second sourcing, higher volume availability, or other business reasons.

Basically, process migration provides a shortcut to a finished layout. Without process migration, a redesign would be necessary—and that takes more time, effort, and risk. It's also a methodology that provides flexibility and portability, and it will allow finished designs to be used as blueprints for multiple technology implementations.

Process migration can help ASIC designers get their new ASIC done faster and with reduced risk and cost. In many cases, the methodology will make it possible to implement an ASIC in a specific process. Essential IP and macro blocks that otherwise may not be available by the foundry can be migrated to a particular process technology.

Process migration also provides a quick way to create a new and more integrated ASIC that reuses many functions of existing separate ASICs, which is an inevitable trend in any established market segment. Another important benefit of migration is risk reduction. Implementing an ASIC in a new technology for the first time involves many risk factors. Not only are there unknowns associated with the new process, but there also are design, verification, and testing risks.

If many of the new ASIC functions were already designed and tested successfully in previous generations, they can be reused and adapted to the new process. This methodology leverages the significant effort that went into the initial design—implementation, testing, and field-proven robustness of previous designs—so current and future implementations will benefit from reduced risk and effort.

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