Electronic Design

RTOS Runs Soft RISC On System-On-A-Programmable Chip

The Nios RISC architecture morphs into version 3 with the latest release of Altera's Nios Development Kit. The kit includes Altera's Stratix high-density FPGA. Kits are also available for other FPGA product lines and include all of the necessary hardware and software for developing a multiple-processor system-on-a-programmable-chip (SOPC).

The kit is relatively easy to set up and configure. It includes a copy of Altera's Quartus II design software with SOPC Builder. Nios processors are configured using SOPC Builder. SOPC Builder is also used to add the standard memory and peripherals and to make connections between devices. Additional components available via the Internet. Software or systems engineers can develop systems based on standard components, while EDA experience is needed to build custom devices. A 10/100-BaseT Ethernet interface is handy for network applications.

Being familiar with the GNUPro toolchain made C/C++ development for the Nios processor straightforward. Accelerated Technology's code|lab Debugger is included, which makes debugging significantly easier. There's also an evaluation version of the Nucleus PLUS real-time kernel.

The debugger works with the Stratix JTAG interface. Nucleus PLUS runs on the 16- or 32-bit Nios architecture. A single Stratix FPGA can support multiple Nios processors. The JTAG support is based on First Silicon Solution's (www.fs2.com) On-Chip Instrumentation (OCI) core. The kit includes First Silicon's FS2 BlackBox Debug Probe.

Nios Version 3.0 is shipping now in the new Nios Development Kit, Stratix Edition, for $995. It runs on Windows 2000 or XP.

See associated figure

Altera Corp.

Accelerated Technology

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