Electronic Design

Second-Generation HardCopy Won't Be Hard To Get

The latest HardCopy structured ASICs deliver up to 2.2 million ASIC gates, 8.8 Mbits of RAM, and up to 350 MHz of system performance. Based on a fine-grained architecture developed by Altera, this family of five HardCopy II devices will deliver a lower cost per gate than the previous HardCopy family. On top of that, these ASICs will extend Altera's reach into wireline and wireless communications, storage, digital consumer, industrial, and military markets.

Interface logic included in the HardCopy II chips supports external memory at speeds of 233 MHz for SDRAM and 250 MHz for RLDRAM II. The chips are fabricated on a 1.2-V, 90-nm process with eight layers of copper interconnect. On-chip interfaces support 1-Gbit/s differential I/O and high-speed interfaces such as 10-Gbit Ethernet (XSBI), SFI-4, SPI 4.2, HyperTransport, RapidIO, and Utopia Level 4 interfaces up to 1 Gbit/s.

Benefits derived from this second-generation series include lower total cost and shorter development time. Also, the devices offer a seamless migration from FPGA prototypes to a production structured ASIC. Altera's Quartis II design software supports the Hard-Copy II family. When using the Stratix II FPGAs, designers can fully validate their design on the FPGAs. Then, they can automatically generate the files and hand them off to the HardCopy Design Center with the software.

Handoff to fully tested prototypes requires eight to 10 weeks. First delivery of prototypes can take place in the third quarter. Volume pricing for lots of 100,000 units starts at $15 each. Nonrecurring engineering charges start at $225,000 for a full turnkey migration, including delivery of fully tested prototypes.

Altera Corp.

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