Electronic Design

Seismic Shifts Await EDA In A “More Than Moore” World

The EDA and semiconductor intellectual property (IP) markets demonstrated good growth and achieved some good exits in 2012. However, one development stands as the most significant, dire, and opportunistic factor that will begin to drive EDA and IP developments in 2013: the semiconductor technology roadmap is running out of road. Moore’s law is beginning to hit that dead end. It won’t occur in 2013, but we’ll certainly begin to see the “final” litho process node looming. It’s not that far off before we hit the wall—in the single-digit nanometer range.

More Than Moore

There is physical evidence that the end of the road is approaching. Advanced node adoption is slowing. Design teams will stay at mature nodes longer, and some will skip nodes altogether to avoid hitting the learning curve more than once. Alternative technologies are taking up some of the slack—most of them by going vertical.

Silicon interposers, FinFETs, and 3D stacked die are all methods for building a new and different path to get beyond the looming dead end, or “more than Moore” as it is called. These technology alternatives will have a substantial impact on the semiconductor industry and the configuration of its supply chain in the years ahead.

In the new more than Moore world, a system-on-a-chip (SoC) becomes a system-in-a-package (SiP). Components of the design will be sourced as separately manufactured silicon slices, all integrated on chip-scale substrates. If you think IP procurement is tricky now, it’s going to become a lot more difficult in the SIP. FinFETs will pose a whole new set of technology adoption challenges as well. Harmonizing these large-scale, independently manufactured subsystems will bring a new set of problems, both technology and business related.

These changes will result in questions that we’ll all need to ponder and answer. Who will take the inventory risk for a new SIP design? Who will take the yield risk for assembly of the system? These questions will create significant business opportunities for those who think about the problem creatively and in the right way. What is that right way going to be?

Crisis And Opportunity

The IP industry has a huge opportunity here. Given the changes that the semiconductor industry will undergo, there will be a crucial need for predictable IP reuse. Standards of IP quality will rise as a must-have on the IP consumer requirements list. There will be an accelerated demand by IP consumers for a uniform quality of deliverables from their IP suppliers. This situation will create opportunity for companies that can measure and report IP quality. All in all, these changes should create a more vibrant industry with higher IP sales and more design starts.  

EDA as a business will undergo tremendous change. Right now, there are too many EDA companies with a product and no sales force. Some will be acquired and some will fail. Although these circumstances are typical for EDA, there will be more acquisitions in 2013, which is a good thing for the industry.

There will be new companies as well, but these EDA entrants will be unlike those in the past. Why? Venture funding for EDA has all but disappeared. The new norm will require technology proof of concept, and shortly thereafter, an exit. The exits will be smaller and backed by bootstrapped and angel-funded enterprises. We’ll still see wealth created out of EDA, but it assuredly will be on a smaller scale. This trend will require the acquiring companies to do more of the heavy lifting associated with scaling the product to volume.

All of these coming changes will demand stronger front-end planning and more careful system design and integration. EDA won’t be a pure play component design business any longer. We’ll need to support the package and system that the component is targeting.

And, here’s just one more prediction for the road. By the end of 2013, the names of the big three EDA companies won’t be the same as they are today.


Mike Gianfagna is the vice president of corporate marketing at Atrenta Inc. His career spans three decades in semiconductors and EDA. He holds a BS/EE from New York University and an MS/EE from Rutgers University. 

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