Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the variability at the cost of additional design efforts. Dual rail solutions appear to be complex, but several area, power, and performance tradeoffs can be made to simplify the design.
Traditionally, the dual rail feature for SoCs and SRAMs has been associated with dynamic power reduction techniques. To use these techniques, chip designers run a part of the IC, called a voltage island, at a lower voltage than the rest of the device in order to reduce dynamic power when the performance requirement of that voltage island is not the primary goal. Similarly, memory designers run a part of the memory, called memory periphery, at a lower voltage than the SRAM-bit in order to reduce dynamic power when the performance requirement is not the primary concern. This technique allows both chip designers and memory designers to reduce active power while still achieving sufficient performance (Fig. 1).
However, as device sizes shrink to the deep nanometer technology nodes of 45 nm and 32 nm, process variability is becoming one the biggest design challenges for the chip designers. Variation in the threshold voltage of the transistor has a strong dependence on the gate area of the transistor ; where ΔV is the variation in the threshold voltage, W is the width of the transistor, and L is the gate length of the transistor. The SRAM-bit takes the worst hit because it has the smallest transistor sizes on the chip, and therefore the most variability.
Another dimension that affects the transistor variability is the chip operating voltage. Device variations worsen as voltage decreases because there is less headroom at those voltages. Even a small variation in the threshold voltage or drive current causes a significant percentage change to the target parameter. While voltage scales with every technology, the threshold voltage of the transistor is not scaling at the same ratio, which means that chip designers have less voltage headroom for the transistors.
Adding to the two previously mentioned issues, SRAM yield is the biggest concern in the deep nanometer era. So even though chip designers want to take advantage of the lower power supply for power reduction, it is desirable to operate SRAM-bit cells at a higher voltage than the rest of the logic circuitry to produce a higher yield.
At first glance, it seems like chip designers will have to give up a lot of power by not operating the SRAM-bit at a lower voltage. However, SRAM bit lines are driven from the periphery drivers. So in reality, most of the active power consumption is in the memory periphery because this is where most of the global drivers are. The only large driver that must be run from the array power supply is the word line driver on the SRAM-bit array power supply.
Chip designers have two options for the SRAM array power supply: either an on-chip voltage regulator (Fig. 2) or an off-chip voltage regulator. The advantage of the on-chip regulator is that it consumes less power because it does not have to drive the huge capacitive load on the board. But remember that it is an analog block, so it needs a stable on-chip power supply in order to provide a stable output.
There is some area overhead for adding dual rail functionality in the memory. The first element of the area overhead is the integrated level shifters in memories. But, the area overhead is less than 2% for wide memories and is not a critical item. The second element of the area overhead is an on-chip or off-chip voltage regulator in addition to the regular power supply. The area overhead of the voltage regulator should be analyzed in context of the total SRAM area on the chip. In most cases, it would account for less than 1% of the total SRAM area.
Another aspect that chip designers and memory designers should consider is the on-chip power supply variations. The memory periphery power supply is coming directly from I/O pads and is shared with most of the digital blocks, so it will have more variations compared to the stable SRAM-bit power supply coming from the voltage regulator. Memory designers need to take this into account.
The design overhead for the dual rail is not as complex. The use of level shifters in the memories is not mandatory. Memory designers can choose not to add level shifters if the difference in the SRAM-array power supply and periphery power supply is small. In that case, some p-channel transistors will have a lower power supply at the gate than at the source. The result is a dc path between power supply and ground, both during read/write operations and while in standby mode. Therefore, the tradeoff is more leakage current for design simplicity. Bottom line is that it’s advisable to build a reliable design and give up some area for the dual rails.