Electronic Design

Strained Silicon-On-Insulator Combats Leakage To Boost Circuit Performance

As companies struggle to push strained silicon technology into the mainstream at the 90-nm process node for greater digital-circuit performance, new variations lurk at 65 nm and below. At these advanced process nodes, performance and power-consumption issues arise due to bulk silicon's higher leakage currents.

Soitec addresses this by combining the strained silicon transistor structures with its SmartCut silicon-on-insulator (SOI) wafer technology. By doing so, not only do circuits get the improved transistors that switch faster, but those devices also will have lower dynamic and static power.

Creating a strained SOI (SSOI) substrate requires the growth of epitaxial silicon-germanium and silicon layers, combined with Soitec's wafer bonding and layer transfer technology. However, the company and others in the industry are working to eliminate the silicon-germanium (SiGe) intermediate layer to produce a true SSOI structure. This would reduce the manufacturing complexity as well as the cost of the wafers.

In the strained silicon, spacing between the atoms in the wafer's plane is greater than it is for unstrained silicon. Biaxial distortion of the crystal lattice changes the electronic band structure of the silicon whereby electron and hole mobility improves by up to 50%. This greater mobility translates into higher operating speeds.

Crystalline germanium and silicon both have the same lattice structure, so in theory, a silicon lattice can be aligned on a germanium template. In practice this doesn't actually happen, since the germanium atoms are 4.2% larger, and the mismatch results in many crystalline defects.

The solution is to use a SiGe alloy as the template since it has a lattice constant in between the constants of silicon and germanium. Soitec epitaxially grows a stack of layers that begins with a buffer layer of silicon and germanium on bulk silicon (see the figure).

In the buffer layer, the fraction of germanium starts at zero at the bottom and gradually goes up to the final value of about 20% (or as much as 50%, depending on the desired end result). On top of this graduated buffer layer, another "template" layer is grown, and its lattice structure matches the lattice at the top of the first buffer layer.

No strain exists in the template layer. So, it's typically called a "relaxed" layer. If this SiGe layer is fully relaxed, the cap layer of silicon deposited on top of it will be optimally strained and have minimum defects.


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