Electronic Design

Structured ASIC Trims NRE Costs For Low-Volume Mil-Aero Chips

RapidChip is LSI's platform for the structured-ASIC arena. The first 20-odd mask layers are laid down in silicon and a power grid is established on a structured-ASIC wafer, but the wafers aren't metallized. Each die has standard layouts of processors, memory blocks, PLLs, SERDES, and so on.

Subsequently, that pre-verified and routed generic silicon is meshed with the customer's application-specific design. To accommodate the customer's contribution, LSI's chips have somewhere between 1 million and 5 million usable ASIC gates. But typically, only four or five mask layers are involved in creating the custom part of the chip. The result is very high integration for a very low non-recurring engineering cost (NRE), and fast turnaround.

In fact, says LSI's John Bendekovic, "The NRE associated with this approach is typically between $50,000 and $200,000. That compares to a cost of over $500,000 just for mask sets for 30-odd layers in a standard ASIC of the same complexity. The mil-aero customer sees a path to a small process geometry with an NRE that looks a lot like it did in the late '80s and early '90s."

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