Electronic Design

Supercomputer On A Chip Promises Teraoperations/s

By applying a computational approach called block-oriented execution, IBM and the University of Texas in Austin are developing a prototype processor IC that can process large blocks of information in parallel.

The project to create a tera-op reliable intelligently adaptive processing system (TRIPS) has four major goals: develop a technology-scalable architecture, craft it so that it's malleable, make it dynamically adaptable, and enable it to handle a diverse array of applications.

The research initially aims to create a processor that uses the TRIPS architecture to provide a large pool of execution resources linked by on-chip thin networks. Sponsored under a DARPA program, the project targets the development of a computing system that outperforms evolutionary architectures on a wide range of applications.

The proposed underlying architecture consists of a grid processor architecture (GPA) composed of a tightly coupled array of arithmetic and logic units (ALUs). Large blocks of instructions are scheduled and mapped onto these ALUs (see the figure). Spatial instruction placement is static, but the execution order is dynamic. The compiler forms large single-entry, multiple-exit regions (hyperblocks) and schedules them to the computational array. To mitigate on-chip communication delays, applications are scheduled so their critical dataflow paths are placed along nearby ALUs.

Along with the grid processors, the TRIPS chip will contain many local register files and instruction and data caches. The GPA array and the on-chip memory system are configurable so the processor can perform diverse tasks.

Completion of a prototype chip is expected in 2005. Such a device will contain about 250 million transistors and operate at a clock speed of 500 MHz. Future process improvements will permit clock speeds to scale to 10 GHz and performance to teraoperations/s.

For details, see www.ibm.com and www.cs.utexas.edu/users/card/trips/home.htm.

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