Electronic Design

Timing Processor Deivers Six Independent Clock Sources

Based on a patented digital timing technology, the TLC28x0 timing processor chip offers designers six independent high-resolution clock synthesizers—more than any other available clock synthesizer chip. Developed by TimeLab Corp., it targets x86 notebook, desktop, and embedded x86 applications.

The timing processor's frequency slewing scheme lets systems continue operations during a frequency change. In contrast, PLL-based (phase-locked loop) clock circuits typically jump frequencies and require a significant amount of time to stabilize. During the frequency change time, system clocks in the PLL systems must be stopped, causing a short delay in system operation.

The TLC28x0 can deliver the six key clocks used in most systems—CPU, SRC, DOT, PCI, AV, and LAN. This lowers overall system cost (see the figure).

The CPU output consists of three differential pairs. The SRC output provides seven differential pairs. The DOT clock consists of a single differential pair plus additional clocks for USB and PCI buses. The PCI clock offers six stoppable outputs and three free-running outputs. The AV and LAN clocks drive some of the PCI timing control signals. And, the chip includes two single-ended reference clock outputs

A 14.318-MHz crystal supplies the clock source for the timing processor. The on-chip oscillator provides the timing signals for all the clock generators. The CPU clock can generate system clocks at rates of up to 400 MHz. It can be adjusted in steps less than or equal to just 21 kHz with a clock-to-clock jitter of 85 ps.

Able to run at up to 133 MHz, the SRC clock can be adjusted in steps of 2.4 kHz with a jitter of just 50 ps. Similarly, the DOT clock runs at 133 MHz and can be adjusted in 2.4-kHz increments, but it has a 250-ps jitter.

The USB clock, derived from the DOT clock, operates at 66 MHz and can be adjusted in 1.2-kHz steps. It also has a jitter of 250 ps. The PCI clock runs at up to 66 MHz as well, and it can be adjusted in steps of 600 Hz or less. Jitter for this clock source is 200 ps.

To support chip setup, TimeLab's Windows-based program enables designers to create and edit timing schemes. The software also monitors system performance and configures the chip.

Housed in a 64-lead QFN package, the timing generator comes in two versions. The TLC2810 is optimized for notebook computers that can operate from a 1.8-V supply. Suiting desktop systems, the TLC2800 operates from a 3.3-V supply. In 10,000-unit lots, the TLC2810 costs less than $3.50 each, while the TLC2800 costs less than $2.50 each. Samples are immediately available.

TimeLab Corp.

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