Electronic Design

Transistor-Jammed Chips Rely On Process Progress

More and more transistors per chip. There's simply no way around it as long as there's a need to create faster and smaller systems that consume less power. This will provide more gates for ASICs and greater amounts of storage for memory chips. It will also yield higher throughput for CPUs, digital-signal processors, graphics engines, and other processors.

Process technologies have evolved dramatically. Cramming a billion or more transistors on one chip has almost become common. Take gigabit-density DRAMs and multi-gigabit flash memories, for instance. Due next month, Intel's next-generation Itanium will integrate 1.72 billion transistors. The dual CPU cores will only utilize 64 million transistors, while the rest will be used to implement over 26 Mbytes of cache.

Many different technologies must come together—lithography, etching, deposition—as well device physics and metallurgy to fabricate and then interconnect these small, faster transistors. In lithography, optical stepper lithography systems using deep-ultraviolet light sources and phase-shift masks now routinely produce features to satisfy the needs of processing schemes based on 90-nm and larger design rules. Many industry analysts say that such systems will be able to deal with features in the 65-nm regime over the next few years (see the figure).

To go even smaller, a simple extension of the technology that immerses the end of the projection lens in a liquid promises device patterning with features below 65 nm. Immersion lithography differs from conventional "dry" lithography, because a liquid (water) replaces the air between the wafer and lens to improve the depth of focus and extend wavelengths to define smaller features.

The immersion scheme uses hyper-numerical-aperture (NA) lenses, which allow the patterning of smaller linewidths without having to develop an expensive new light source. It also enables the extension of 193-nm lithography to the 45-nm node. ASML's Twinscan XT:1250i uses a 300-mm-wafer, dual-stage design that combines the improved depth of focus of immersion tools with the minimum resolution of dry lithography systems.

It's one challenge to define the features using lithographic systems. But many more challenges surface when it comes to etching the features and depositing films that in many cases are just a few atoms thick. Shrinking transistor dimensions pose many hurdles when it comes to creating the transistor structures: very shallow source and drain regions; tiny gate regions; and multiple opportunities for impurities to migrate into areas where they're not wanted.

When transistor dimensions shrink, operating voltages must also drop to prevent damaging "voltage punch-through" effects. The potential difference between the two conducting regions causes the oxide dielectric that separates the two regions to break down. What results is a short-circuit path between the two conducting regions.

The easiest solution lowers the operating voltage further to reduce the potential difference. Lower voltages may not completely turn off the transistors' gates, so the transistors become more "leaky." This leads to higher-than-desired standby currents. On chips with large numbers of transistors, such as microprocessors or static RAMs, this could cause idle currents of 5 to 10 A for a CPU and hundreds of milliamps for a memory chip.

As gate dimensions shrink further to 65 nm and to 45 nm, leakage currents will rise to levels where it may become hard to discern whether the transistors are on or off. To prevent that, designers are working on new transistor structures with multiple gates to ensure the transistor can turn off and minimize leakage current. Known as FINFETs, these transistors employ multiple gates to surround the channel on two or three sides, rather than just covering the top surface of the gate region. By surrounding the gate, designers can turn off the channel, providing a better on/off margin.

Some vendors use silicon-on-insulator (SOI) to reduce leakage currents and boost performance. By isolating the active layer from the substrate, SOI eliminates many of the parasitic losses that plague digital circuits as they're clocked at ever higher frequencies.

The isolated active layer enables transistors to switch faster. Spacing between transistors can be reduced because fewer interactions occur between devices. Chips can then operate at lower power levels for the same clock speed as their standard CMOS counterparts. Or, they can be clocked at about 120% of the speed of standard CMOS versions. As process design rules drop to 65 nm and smaller, SOI should play a growing role in high-performance circuit fabrication.

Just as SOI technology has changed since the first silicon on sapphire circuits emerged in the 1960s, so has the transistor gate structure. It has moved from metal gate to silicon gate and now back to new metal-gate approaches to eliminate the series capacitance stemming from polysilicon depletion. Such capacitance is becoming an increasingly larger percentage of the total gate capacitance, and it limits transistor performance. But challenges do crop up because n- and p-channel transistors would typically require different metals to best match the "work functions."

In a presentation at the recent IEEE International Electron Devices Meeting in San Francisco, researchers from L2MP, STMicroelectronics, and Philips Semiconductors showed off the ability to co-integrate different MOSFET configurations (general purpose, low power, high speed, buffer transistors) fabricated via a standard process. The technique they developed—poly-gate replacement through contact hole (PRETCH)—lets them replace initial polysilicon gate and/or gate oxide by any gate-stack desired. It accounts for multi-Vt control, multi-oxide deposition, and metal-gate integration implementation challenges.

The road to transistors with higher performance takes many paths. With strained silicon technology, the atomic lattice structure of the silicon gate region is actually strained (compressive strain for p-channel devices and tensile strain for n-channel devices), so holes and electrons have greater mobility. In addition to just straining the silicon, a few companies have introduced germanium atoms into the atomic lattice to further enhance the mobility.

TAGS: Intel
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