Electronic Design

Trends Tip The Scales In Favor Of SiP Versus SoC

The pro and con arguments regarding SoCs versus SiPs are familiar. This discussion is becoming increasingly germane as the electronics industry struggles to meet cost and time-to-market demands for highly miniaturized and complex electronics.

In the last decade, numerous trends emerged that greatly impacted the way we design electronics. Not only are products highly advanced in terms of their feature set and form, but many have a shelf life of under a year.

Add to these trends the rising cost and time-to-market penalties associated with introducing new SoCs to market, the significant technical advances made in the area of Known Good Die, and a highly fragmented application market being served by a staggering range of options, and it becomes quickly apparent that the electronics industry has undergone a profound transformation over the past decade. This transformation has tipped the SoC/SiP debate in favor of SiPs in a large class of applications.

For example, one major concern with using SoCs is cost. A state-of-the-art SoC design for a consumer device can easily reach $10 million once all of the required design engineering, verification, and tooling costs (photomasks) are taken into consideration. Assuming the manufacturer will sell 1 million such devices, the amortized nonrecurring engineering (NRE) cost per device is then $10.00.

In many cases, this exceeds the per-unit manufacturing cost of the chip. So, the NRE is a significant component of the bill of materials, considering that a consumer product might have margins of only a few dollars at the wholesale level. This cost penalty is further exacerbated if the product has to be redesigned shortly after.

A less obvious but equally important penalty is the time-to-market that is lost as a result of the long design cycle associated with an SoC. Depending on complexity, this can run from six months in a relatively simple consumer product to 18 months or more in a complex networking chip.

Since SoC price and volume are inversely related, designers may be willing to take the risk associated with designing and manufacturing an SoC for high-volume standard products, such as video game consoles. However, the electronics industry is becoming more fragmented, as evidenced by a broad range of products, such as cell phones, MP3 players, digital video cameras, and digital still cameras. Additionally, product life cycles continue to shorten. In these instances, not only are SiPs more cost-effective for integrating greater functionality in smaller form factors, but they also can be developed and made available in a one- to two-month cycle.

Other key trends weighing in favor of SiPs include die-thinning technologies and 3D stacking techniques, which enable a multichip package to have the same final form factor as a single-chip device. Individual chips in an SiP can now be tested, either in bare die form or in a "micropackage" form, prior to integration into an SiP module.

This enhanced testing capability addresses one of the key early stumbling blocks of SiP adoption—specifically, failure of the entire system due to a failure of one of the devices in the stack. Another key benefit is that SiPs, by their nature, have a highly flexible and scalable platform. The ability to design in the third dimension provides engineers great freedom in how they can envision their products. For instance, imagine a cell phone taking the form factor of a pen.

In summary, a confluence of industry trends over the last decade has made SiPs a highly attractive alternative to SoCs in a number of applications. There are still instances where SoCs best meet market requirements. But in an increasing number of electronic products, SiPs are the preferred solution, not only because of the inherent cost and time-to-market advantages, but also because SiPs will eventually enable a new wave of product innovation.

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