Electronic Design

Ultra-Thin Gate Oxide And Direct Tunneling Improve Flash Write/Erase Performance

The combination of an ultra-thin gate oxide and a novel sidewall control-gate structure that suppresses gate-leakage currents promises high-speed write/erase operations at low voltages. This new structure, developed by Fujitsu Laboratories Ltd., Atsugi, Japan, overcomes some of the scaling limitations of previous floating-gate flash memories (see the figure).

Direct tunneling has been used to overcome some of the problems, but it still requires a relatively high programming voltage. Ultra-thin direct tunneling, however, allows the use of lower control voltages. As a result, the process can be scaled so that it can be used in higher-capacity memories.

Described in paper 11.6 by company researchers at last month's IEEE International Electron Devices Meeting in Washington D.C., the structure also is completely compatible with standard MOSFET processing Consequently, there are no nanocrystal or interface state issues. It permits full control of the device's parameters—coupling between the floating gate and the control gate, or the overlap between the floating gate and source-drain extensions. These parameters let the user set the device performance (operating voltage or retention time).

To suppress the leakage current, the researchers did two things to the direct-tunneling structure. First, they formed a self-aligned sidewall control gate. Such a construct removes the spatial overlap between the floating gate and the source-drain extensions. This suppresses the leakage current between the gates.

Second, a leakage stop barrier is formed by the n+ floating gate and the highly doped channel due to a large built-in potential. This barrier reduces the thermally assisted tunneling leakage current from the floating gate to the channel. By lowering the leakage current, the retention time can therefore be increased.

In ultrathin direct-tunneling memory cells (oxide thickness of 1.9 nm), the write time can be trimmed to just 50 ns when a 5-V bias is used. By comparison, a typical thick-oxide (2.5-nm) device would have a write time of about 2 µs.

In the erase mode, the direct-tunneling device has less of a threshold voltage shift, and it should be able to endure more write cycles than thick-oxide devices—projected at 108 or 109 write-erase cycles.

To contact the researchers, fax N. Horiguchi at +81 46-250-8804, or e-mail [email protected].

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