Electronic Design

USB 3.0—The Next-Generation Interconnect

Imagine that your flight from San Francisco to New York takes off in three hours. During the long flight, you’d love to watch the new season of your favorite show or a movie that a friend recommended, but you might think there’s not enough time to complete the download before you have to leave.

Thankfully, technological innovations are happening at a pace that enables users to get the content they want a lot faster. One such evolution is that of the most universal and ubiquitous interface—the Universal Serial Bus (USB). The new USB 3.0 specification supporting SuperSpeed rates is here and promises to be the panacea to such situations.

Thanks to the Internet and the communications revolution, an enormous amount of content is being generated, processed, and consumed at a staggering rate. In parallel, mass storage technologies are seeing significant innovation. Storage is becoming inexpensive and densities are increasing, driving content sharing. Users no longer worry about conserving hard-drive space.

Yet so strong is the need for a faster interconnect technology that several technology leaders have come together to solve this problem in an elegant and seamless manner. The USB Implementers Forum recognized this urgent need for a next-generation interconnect technology and ratified USB 3.0 in November 2008.


USB 3.0 is the next stage of USB technology. Its primary goal is to provide the same ease of use, flexibility, and hot-plug functionality but at a much higher data rate. Another major goal of USB 3.0 is power management. This is very important for “Sync & Go” applications that need to trade off features for battery life.

Chipsets are expected to begin shipping in 2010, with broad deployment in 2011. A variety of USB 3.0-based products including PC motherboards, hard drives, PCI Express (PCIe) add-on cards, and cameras were showcased in industry events in 2009, and more products are expected to be released in early 2010.

USB 3.0 heralds an all-new wave of application usage models and is expected to deliver actual throughput greater than 3 Gbits/s (raw signaling speed of 5 Gbits/s), which is more than 10 times higher than that of Hi-Speed USB. Initially, USB 3.0 will target the PC market and devices requiring high rates and volumes of data transfer, such as external storage, consumer electronics, and communications products with increasing amounts of storage.


The USB 3.0 interface consists of a physical SuperSpeed bus in addition to the physical USB 2.0 bus. The USB 3.0 standard defines a dual simplex signaling mechanism at a rate of 5 Gbits/s. This enables simultaneous transfer of data to and from the device as opposed to the single duplex unidirectional USB 2.0 bus.

The architecture is designed to be electrically and mechanically backward compatible with USB 2.0, so a USB 3.0 host would communicate with a device at the fastest signaling rate supported by the device. Conversely, a USB 3.0-compliant device would seamlessly function at the USB 2.0 signaling rate when plugged into a USB 2.0 host.

In addition to a signaling rate that’s 10 times faster than USB 2.0, USB 3.0 supports a significantly more efficient transfer model, such as asynchronous notifications replacing the polling model of USB 2.0. As an example, when the USB 3.0 host initiates a transaction, the device may respond with Not Ready (NRDY) if data or buffer space is not available. Later, when the device can honor the request, it will report an Endpoint Ready (ERDY) status to the host.

A USB 2.0 host broadcasts packets to all enabled downstream devices, forcing all devices to decode the address received with every packet. In contrast, a USB 3.0 host unicasts packets only to the target device by embedding routing information in transmitted packets, which an intermediating hub decodes.

This model of unicast packets allows inactive devices to remain in a low-power state, and it’s one of the several power-saving techniques implemented by USB 3.0. The USB 3.0 specification (see the table) also lets devices draw up to 900 mA when attached to a host, which is significantly higher than the 500-mA limit set by USB 2.0.


The layered PCIe architecture and the OSI model inspired the USB 3.0 architecture (Fig. 1). It has a physical layer (PHY), link layer, and protocol layer. The PHY includes the connection between a host and a device or a hub and a device. Similar to the PCIe PHY, the USB 3.0 PHY includes 8b/10b encoding/decoding, data scrambling and descrambling, and serializing and deserializing functions. 

The link layer maintains link connectivity and ensures data integrity between link partners by implementing error detection. Packets are created in the link layer, and link commands are issued. The protocol layer manages end-to-end data flow between a device and a host.

Like USB 2.0, the SuperSpeed bus carries data, address, status, and control information. Four packet types are defined. Two of them, the Transaction Packet (TP) and Data Packet (DP), remain the same as in USB 2.0. Two additional packet types, Isochronous Timestamp Packet (ITP) and Link Management Packet (LMP), are newly introduced by USB 3.0.


USB 3.0 provides enhanced power-management capabilities to address the needs of battery-powered portable applications. Two “Idle” modes (denoted as U1 and U2) are defined in addition to the “Suspend” mode (denoted as U3) of the USB 2.0 standard.

The U2 state provides higher power savings than U1 by allowing more analog circuitry (such as clock generation circuits) to be quiesced. This results in a longer transition time from U2 to active state. The Suspend state (U3) consumes the least power and again requires a longer time to wake up the system.

The Idle modes may be entered due to inactivity on a downstream port for a programmable period of time or may be initiated by the device, based on scheduling information received from the host. Such information is indicated by the host to the device using the flags “Packet pending,” “End of burst,” and “Last packet.” Based on these flags, the device may decide to enter an Idle mode without having to wait for inactivity on the bus.

When a link is in one of these Idle states, communication may take place via low-frequency period signaling (LFPS), which consumes significantly lower power than SuperSpeed signaling. In fact, the Idle mode can be exited with an LFPS transmission from either the host or device.

The USB 3.0 standard also introduces the “Function Suspend” feature, which enables the power management of the individual functions of a composite device. This provides the flexibility of suspending certain functions of a composite device, while other functions remain active.

Additional power savings are achieved via a latency tolerance messaging (LTM) mechanism implemented by USB 3.0. A device may inform the host of the maximum delay it can tolerate from the time it reports an ERDY status to the time it receives a response. The host may factor in this latency tolerance to manage system power.

Thus, power efficiency is embedded into all levels of a USB 3.0 system, including the link layer, protocol layer, and PHY. Figure 2 compares the system power consumed during a SuperSpeed and a Hi-Speed data transfer.

A USB 3.0 system requires more power while active. But due to its higher data rate and various power-efficiency features, it remains active for shorter periods. A SuperSpeed data transfer could cost up to 50% less power than a Hi-Speed transfer. This is crucial to the battery life of mobile handset devices.


A new model of “Streams” supports the SuperSpeed raw data rate. Multiple buffers of data may be set up and organized as Streams to a single bulk endpoint. Up to 64k Streams may be multiplexed per endpoint.

Streams are available on both IN and OUT endpoints, and each Stream is tagged with a Stream ID. Both the host and the device can establish the “Current Stream” associated with an endpoint. The host or device may also truncate a Stream (Fig. 3) when necessary.

Streams make it possible to realize an out-of-order execution model required for command queuing. Currently, the USB Mass Storage Class (MSC) standard is the protocol of choice to communicate with storage devices.

But the MSC protocol imposes certain limitations. For example, an MSC host can only issue one command at a time. Also, the host and device require frequent intervention during command processing. These inherent restrictions lead to significant bottlenecks in MSC transfers. They limit throughput in current USB 2.0 systems and would severely impair throughput in future USB 3.0 systems.

The concept of Streams would enable more powerful mass storage protocols. A typical communication link would consist of a command OUT pipe, an IN and OUT pipe (with multiple data streams), and a status pipe. The host would be able to queue commands, i.e., issue a new command without waiting for completion of a prior one, tagging each command with a Stream ID. As a result, Streams would be essential to alleviate MSC bottlenecks.


Several other serial communication standards boast a data rate similar to that of USB 3.0. For example, PCIe Gen 2.0 has a data rate of 5 Gbits/s, and Serial ATA (SATA) III has a data rate of 6 Gbits/s. Although PCIe inspired the USB 3.0 PHY architecture, several key distinctions exist.

The USB 3.0 PHY must implement an equalizer required to compensate for cable loss. This enables USB cables to be as long as 3 meters. The PCIe and SATA PHYs do not have such an equalizer. The LFPS feature described earlier is also unique to the USB 3.0 PHY. And, a PCIe link may consist of multiple lanes (i.e., pairs of transmit and receive differential lines) to increase bandwidth, whereas a USB 3.0 link supports only a single lane.

Of these three interfaces, only USB enables true plug and play. The SATA standard does support hot-plug, but it’s contingent on the SATA controller functioning in Advanced Host Controller Interface (AHCI) mode.

PCIe is typically used to connect peripheral function cards (such as graphic cards) directly onto the motherboard of a PC. SATA is an interface of choice for mass storage devices such as hard-disk drives and optical drives. Hence, most PCs integrate a SATA host adapter. USB, on the other hand, serves as a general-purpose SuperSpeed or Hi-Speed bridge between a host and virtually any interface.

USB 3.0 also lends itself well to be an alternative interface for transferring video given the increased bandwidth. This could herald some interesting applications in the digital living room, including TV, set-top boxes (STBs), monitors, and gaming consoles. The key advantage of USB versus video interfaces like VGA, DVI, DisplayPort, and HDMI is its ubiquity. With HDCP 2.0 including USB as one of the interfaces, USB 3.0 also can enable content protection. Another benefit is the fact that USB is royalty free.


Charging over USB has inherent benefits compared to having discrete chargers for every device. Not only does it lower manufacturing cost by limiting vendor-specific chargers, it also has a significant impact on the environment in the long run by eliminating the need for individual chargers for each USB-based device.

USB 3.0 hosts and hubs enable the battery charging schemes as defined by the USB Battery Charging Specification. It currently defines three types of usage modes for charging:

  • Host charger: A host charger is a USB 2.0 host that provides up to 500 mA to a downstream port and implements charger detection. A Hi-Speed device may draw only up to 900 mA from the host charger.
  • Hub charger: A hub charger is a USB 2.0 hub that provides up to 500 mA to a downstream port and supports charger detection. The charging functionality is very similar to a host charger.
  • Dedicated charger: A dedicated charger provides power over the USB interface but does not enumerate the device. The charging current is limited to 1.5 A.

The specification also provides for dead battery charging, allowing a dead or very weak battery to draw up to 100 mA from a host or hub until it is charged to a reasonable threshold. USB 3.0 systems will continue to leverage the distinct advantage of being able to charge over USB.

USB 3.0 is anticipated to be the ubiquitous solution for many bandwidth-hungry applications. Its evolution from the highly successful USB 2.0 is fueled by increasing multimedia consumption demands and higher-density storage technologies.

USB 3.0 is an enabling technology, but it will still have to prove that it can survive the inflated expectations that precede mass market adoption. Given USB’s track record, the electronics industry can count on the fact that the day is fast approaching when end users can get all the content they want on their way to the airport in less than a minute.

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