Many network designers are discovering that the fastest and easiest way to process packets at the ever-increasing line speeds is to offload the packet classification function to a coprocessor. One of the best coprocessors for this function is a content addressable memory (CAM), also known as an associative memory. A CAM eliminates the massive amount of time normally spent by an NPU in search routines when attempting to identify and classify packets. With the right CAM, processing speeds of well over 100 million packets/s can be achieved.
A CAM is a special RAM, usually SRAM, although DRAM versions are available too. Each bit of storage has an associated bit comparator and, in some cases, an OR gate (see the figure). This combination lets the CAM compare an external input to the content of the RAM. Data stored in the CAM cells, like source and destination addresses, is compared to an external data input. The packet header field or a part thereof is provided to the CAM, which simultaneously compares it to all of the CAM contents. Then, if a match is achieved, the packet header provides an output indication. The operation of the CAM is the reverse of a regular RAM, where the input is an address and the output is the data. In a CAM, engineers provide the data and the CAM returns the address that will be used to develop and initiate forwarding instructions to the processor.
CAMs may produce more than one match during a comparison. In such cases, the lowest address of those matches is usually provided to the output. But this is handled differently in various commercial CAMs.
There are two types of CAMs: binary and ternary. Binary CAMs make only 0 and 1 comparisons, while ternary CAMs compare 0, 1, and X (don't care) states. Ternary CAMs are most efficient because individual bits or fields of bits may be ignored or masked in a comparison. Some CAMs also feature "greater than" or "less than" comparisons.
Sources of commercial CAMs include Kawasaki LSI, Lara Networks, MOSAID, Music Semiconductor, SiberCore Technologies, and Virage Logic.