Electronic Design

Z-RAM Steps Into SRAM's Territory

Today's system-on-a-chip (SoC) designers face a myriad of challenges, not the least of which is shrinking the die size when memory dominates chip area and cost. And with each subsequent generation of silicon, that

domination is steadily increasing. The reason for this is simple. As processors continue to get faster, main memory grows larger. In fact, with each succeeding generation, main memory access takes longer in terms of processor cycles.

With memory latency closely tied to overall system performance, it s easy to see how the designer s choice of memory technology can have a dramatic impact not only on system performance, but on overall cost as well. SoC designers are now being forced to find alternate options to some of the more common types of embedded memory.

So what are the memory choices available to today s SoC designer? SRAM embedded memory traditionally has been the designer s option of choice for fast memory. Yet its speed comes at the expense of both cost and silicon area. Other alternatives such as embedded DRAM or zero-capacitor DRAM (Z-RAM) technology have the benefit of lower costs, though they have higher latency and are typically used further from the processor.

In spite of this, using more memory closer to the processor can generate a performance advantage, even if the raw memory latency is higher. Because of their potential for both lower cost and higher performance, alternative memories like DRAM and ZRAM are now replacing SRAM in what was traditionally considered sacred SRAM territory.

Z-RAM, a new player in this market, is perhaps the less well known of the two alternative memory options. As a capacitor-less, single-transistor DRAM technology that exploits the intrinsic floating-body effect of silicon-on-insulator (SOI) devices, its cell size can be half the size of an embedded DRAM transistor plus capacitor cell. Also, it s less than a fifth the size of a six-transistor SRAM equivalent.

Z-RAM s small cell size results in higher memory density, allowing more memory in the same silicon real estate or the same amount of memory in proportionally less space. In addition to reducing cost, the small cell size reduces the probability of memory cell alpha particle hits, which improves soft error rate (SER) performance up to 10 times over SRAM.

The savings don t end there. Relative to embedded DRAM, the Z-RAM cell requires no special materials or extra mask/ process steps. And because ZRAM doesn't require a capacitor cell, the additional process complexity dictated by an embedded DRAM isn't required. The result is lower processing costs, faster manufacturing cycle times, and higher yields.

Furthermore, Z-RAM s simple cell layout and process improves scalability and sets the stage for the realization of even greater benefits as smaller technology nodes evolve. Z-RAM technology also features reduced standby power, which can be orders of magnitude lower than SRAM. Depending on the application and array configurations, Z-RAM standby power can be as low as 10 µA/Mbit of memory.

These benefits make Z-RAM a compelling solution for SoC and microprocessor unit (MPU) applications built on an SOI process. If the amount of memory space used in a bulk-technology-based SoC or MPU is significant (e.g., greater than 25% of total SoC or MPU area), the savings provided by a Z-RAM solution can more than offset the cost of converting from a bulk to an SOI process. Coupling that savings with the intrinsic benefits of SOI over bulk such as lower power, better SER, and faster transistors often can justify a transition from bulk to SOI.

Different memory solutions, as well as different implementations of a given memory solution, may be required depending on the application in question. Selecting a memory solution that can accommodate increases in processor speed without severely impacting system performance or overall cost is essential.

While SRAM has been the traditional choice for fast memory, alternatives such as DRAM and more recently, Z-RAM now give designers a number of compelling benefits that may reduce memory cost while also increasing performance.

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