Monrovia, Calif., USA: Version 12.53 of Tanner EDA’s HiPer Silicon full-flow analogue and mixed-signal design suite includes HiPer Simulation AFS, which adds schematic capture, dual circuit simulators and waveform probing to the mix. It also features Tanner Analog FastSPICE (T-AFS)—a combination of the Berkeley Design Automation Analog FastSPICE platform and Tanner EDA’s S-Edit schematic capture and W-Edit waveform analyser.
With two Spice simulators, HiPer Simulation AFS can maintain performance and productivity levels even for large netlists. According to Tanner EDA, T-AFS runs five to 10 times faster, on a single core, than traditional Spice simulators. Users can drive the T-AFS simulator directly from S-Edit, achieving the speeds and accuracy necessary for nanometre design. Simulation results are displayed automatically in W-Edit for interactive viewing, measuring, and analysis.