Electronic Design


Despite its general commoditization, the RTL-to-GDSII flow still sees improvements and new efficiencies. At this year’s DAC, vendors will show a number of tools and technologies intended to make your life easier as you get your design ready for prime time.

One of the more venerable EDA vendors is Tanner EDA, which will be in booth 1114 at DAC with Tanner Tools Pro v12.1. Version 12.1 is the latest edition of Tanner’s integrated suite of IC design tools for analog/mixed-signal designs, ASICs, and MEMS devices. There are numerous enhancements throughout the suite. For example, the S-Edit schematic-capture tool now offers scalability to handle very large designs. It offers a hierarchical connectivity display as you navigate the schematic’s hierarchy. New capabilities have also been built into the T-Spice simulator, L-Edit physical-layout tool, and HiPer Verify DRC tool.

On the IP front, check out Kilopass, right next door to Tanner in booth 1117. Kilopass is a supplier of embeddable, non-volatile memory IP that’s implemented in a standard CMOS process. They’ll be showing customer success stories revolving around consumer ICs, mixed-signal designs, secure ID storage, and embedded boot-code and firmware storage.

Even more broadly concerned with IP is Chip Estimate Corp. (booth 4055) and its new integrated chip-planning portal at http://www.chipestimate.com. Visitors to the site can use a “rank-by-relevance” search engine to find IP components and view comprehensive datasheets. There’s over 4000 components in the online catalog from over 150 IP suppliers. Users can build lists of interesting IP and then import these lists into a free copy of Chip Estimate’s InCyte tool, which estimates the overall chip size, power, and leakage. Chip Estimate recently acquired the VCX IP database from Beach Solutions while retaining its IP partner relationships.

Don’t miss Zenasis Technologies at booth 3027 for a look at the company’s design optimization tools and technologies for cell-based IC designs. Zenasis’s hybrid optimization technology analyzes designs at the logic, physical, and transistor levels and employs multiple optimizations to maximize quality of results.

As Electronic Design columnist Bob Pease might say, “what’s all this predictive development stuff, anyhow?” You can find out at Atrenta’s DAC tutorial on Wednesday, July 25 from 2 to 5 pm. There, you’ll be able to see how Atrenta and Freescale Semiconductor partnered on the development of a 3G cellphone chip using Atrenta’s predictive-development technologies. Atrenta’s SpyGlass LP tool can be used on similar designs to minimize on-chip power consumption and make design closure a more predictable process.

For much more on RTL-to-GDSII tools and technologies at DAC, check the July 6 issue and its full DAC preview at www.electronicdesign.com, ED Online 12493

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