MUNICH, March 7 — Each segment of the electronics industry has its Really Big Show, the exhibition and/or conference you don't want to miss. For the electronic design automation (EDA) industry, the U.S. has the Design Automation Conference each June. But in Europe, the big EDA event is the Design Automation and Test in Europe Conference, or DATE. The conference alternates each year between Munich and Paris, and this year's lot falls to chilly Munich to host Europe's EDA community.
Here in Munich it's snowing lightly, a peaceful prelude to a busy week of product and technology announcements at the ICM Messe Trade Fair. Before the conference began, a smattering of announcements made their way to me before leaving for Munich and here they are, from system-level technology on up to design closure and beyond.
Many years ago, European designers took to VHDL. It wasn't only because it was the best alternative they had at the time, either. Europe's IC designers have long had a system-level mindset, much more so than their American and Asian counterparts. It's taken decades for Verilog to catch up to VHDL in terms of system-level constructs, and many ideas that are now being codified in SystemVerilog are loosely borrowed from VHDL. So it's fitting that DATE 2005 should have a pronounced electronic system-level (ESL) feel.
CoFluent Design's flagship product, CoFluent Studio, has in the past been limited to early analysis of a single parameter, which was resource usage. In the new Version 1.1, CoFluent Studio for System Architecting also supports power consumption, memory footprint and cost. Each index can be observed and analyzed at all levels of the system's hierarchical structure: locally (for one element of the hierarchy) or globally (for the whole system).
As CoFluent Studio generates and runs executable SystemC models of whole systems, it automatically computes and displays the evolution of the above major performance indices over time, locally and globally, providing min, max and average values. As a result, the tool enables designers to analyze the impact of design decisions on the system's performance. Through display tools and a control panel for global performance analysis, designers can try and compare different scenarios, explore various architectures and pick the right one.
For many designers, the building of a virtual prototype has become an important part of their design flows. At DATE, VaST Systems Technology is launching its Peripheral Device Builder (PDB) tool, which enables its customers to quickly develop peripheral devices such as interrupt controllers, DMA VaST engines, timers, clocks, memory controllers and many others.
VaST's customers use the company's CoMET and METeor ESL environments, virtual processors and bus models to create virtual system prototypes that are accurate in terms of functionality and timing. Each of these virtual systems has many peripheral devices that need to be modeled. PDB complements VaST's Platform Constructor Tool (PCT) and now enables its customers to build peripheral devices and then rapidly integrate them directly into platforms.
Peripheral Device Builder, currently in use by early adopters, is available for general release March 31, 2005 with one-year time-based, node-locked pricing of $25,000.
In addition, VaST is announcing version 5.7 of its CoMET ESL environment, which enables developers to create virtual system prototypes in software working from high-level specifications as early as the architectural phase. The new version supports VaST's fastest models, built with the company's new generation of simulation technology, while still providing for integration of and co-simulation with previous generations of VaST models. CoMET now also supports SystemC models and can cosimulate them with VaST's model formats.
CoMET 5.7 is currently being used by early adopters and is available for general release March 31, 2005 with pricing starting at $30,000 for a one-year, node-locked license.
Getting from an ESL design representation to implementation is a matter of concern for many designers. But tools and methodologies for this have existed for some time in the programmable-logic space, and at DATE, Atmel and Celoxica will announce a collaboration that extends designers' options. The pair is bringing ESL design to a family of dynamically reconfigurable processors currently under development at Atmel. These new backend tools are being developed for a new generation of processors based on Atmel's FPSLIC technology that is planned for introduction later this year.
Tools from Celoxica's ESL portfolio, the DK Design Suite and Agility Compiler will synthesize hardware accelerators from highly complex algorithms described in C or SystemC. Celoxica will also provide its hardware/software co-design technology and board-level integration technology to offer Atmel customers a seamless implementation flow. The tools are new to the industry because they allow for dynamic reconfiguration.
In other DATE news, Celoxica will announce its latest programmable SoC prototyping and development platform. The RC250 extends Celoxica's RC series of high-performance FPGA development boards for complex system design and is available with an out-of-the-box suite of ESL design software, IP and system-level APIs for rapid system exploration and implementation.
The RC250 package offers designers a complete hardware/software desktop environment for complex system development. Expressly designed for the rapid creation of high-performance, high-throughput multimedia and communications applications, the RC250 has a feature rich array of peripherals including analog and digital video I/O, two channel gigabit Ethernet and USB2.0. Also supplied is a comprehensiveplatform support library (PSL) that allows easy access to the board-level features from the ESL. System-level APIs supplied with the RC250 enable hardware/software co-design and architectural exploration of partitions, and encourage IP reuse by abstracting the specific board-level detail away from the application code.
Pricing for the RC250 starts at $7,650 for the RC250 Professional and $9,000 for the RC250 Expert.
Half of the battle of getting a design functionally verified is ensuring that as much of the design has been exercised as is possible. TransEDA is introducing what it calls Expression Coverability, a major addition to its Verification Navigator suite of HDL verification tools.
Measurements of statement and branch coverage are no longer considered sufficient for the verification of HDL design representations. Achieving even 100% statement and branch coverage does not ensure that a design has been sufficiently exercised. Best practices now demand the use of coverage for expressions in conditional statements, which requires analysis at a greater level of detail. Using technology that has been proved by aerospace industry experts to be equivalent to Modified Condition/Decision Coverage (MC/DC), mandatory in safety-related applications, TransEDA's Focused Expression Coverage (FEC) metric now delivers this level of accuracy.
To boost the effective use of FEC, Expression Coverability Analysis augments the Coverability Analysis capability of the Verification Navigator tool set. Expression Coverability provides automatic and in-depth analysis of conditional expressions for designs written in Verilog, VHDL and mixed languages. It automatically and transparently invokes an embedded formal engine to quickly ferret ouit uncoverable expression terms as well as coverable terms that have not been exercised.
Design Coverability Analysis is available now as an option to VN-Cover on platforms running the Solaris or Linux operating systems.
Cadence's recent acquisition of Verisity, its e verification language, and the associated methodology has made for uncertainty in some circles regarding Cadence's intentions in terms of supporting the e language. That's not stopping Prosilog SA from integrating Yogitech's e verification component (eVC) for the Open Core Protocol (OCP) in Magillem, its platform-based design environment.
As any other IP block within Magillem, the eVC is imported, configured and connected to the design under test (DUT). Yogitech's eVC is registered in the Magillem Verification IP list, and the user can select and parameterize the OCP interfaces required for the test (OCP 2.0 or 1.0, master or slave). Then Magillem provides an assistant, compatible with the eRM (e Reuse Methodology), which generates the e configuration code. It allows users to easily set all the parameters of the verification agents (master, slave or monitor) for configuration, monitoring and bus-functional model behavior. The mapping of the e variables on the HDL signals can also be changed.
Finally, Magillem generates the platform interconnection code (in VHDL, Verilog or SystemC), and the bus matrix, bridges, protocol wrappers or multi-abstraction level adapters, provided by Prosilog both as synthesizable or simulable models. Any HDL compiler can use all of this generated code to simulate the DUT.
Highly complex SoC designs must reach signoff from a number of perspectives. Power integrity is on the minds of many designers, and Apache Design Solutions established itself as a leader with its flagship RedHawk analysis tool. Apache's next-generation dynamic power analysis and verification tool, RedHawk-EV, provides increased coverage for design weakness identification and exploration. It performs automatic supply-noise repair for power closure sign-off, and also offers higher capacity for transient simulation of SoC designs.
RedHawk-EV combines the new EV technology and Apache's full-chip Vectorless-Dynamic solution with network structural and timing analysis for extensive coverage of the power space and exploration of physical design weakness. By precisely identifying the locations of design weaknesses and their impact on dynamic voltage drop and ground bounce, RedHawk-EV allows designers to not only verify potential power-related functional and timing behavior, but also avoid excessive over-design.
The EV technology can also automatically repair the cause of supply noise to eliminate dynamic and static "hot spots," which can produce timing failures and low yield. The EV technology offers targeted wire fixing, including non-uniform grid re-sizing to meet the needs of high-power regions.
RedHawk-EV will be available in the second quarter of this year. It is licensed on the Linux, Sun Solaris, and HP-UX operating systems. All existing RedHawk-SDL customers will be automatically upgraded to RedHawk-EV.
From the signal-integrity (SI) perspective, Cadence is announcing customer ratification of its low-power enhancements to the Encounter CeltIC Nanometer Delay Calculator (NDC). CeltIC NDC takes advantage of Cadence's effective current-source model (ECSM) to support signoff analysis of low-power designs that include multiple supply voltages and multi-threshold cells. This includes accurately modeling the combined impact of crosstalk and supply voltage (IR) drop on timing and noise immunity by reading IR drop information from Cadence VoltageStorm power-analysis tool.
CeltIC NDC also includes a technology called path-based alignment (PBA) that significantly reduces SI delay pessimism, often by a few hundred picoseconds or more, resulting in much faster SI closure. Other capabilities include reporting of potential doubling clocking failures, Spice deck generation of critical paths (including SI) and a 30% reduction in memory usage. Significant ease-of-use improvements have also been made to the commands, reporting and diagnostic capabilities.
Development of a full-chip test architecture is a task that often stymies design teams, but Cadence's Cadence Encounter Test Architect is designed to do just that. It includes a unified compiler-based methodology for full-chip test, resulting in faster development of a higher-quality test infrastructure than is currently possible with point test tools.
Based on a unique test infrastructure compiler, Encounter Test Architect supports a unified methodology for specifying, compiling, and verifying full-chip test. This includes scan, compression, memory BIST, on-product clock generation, boundary scan, and I/O test.
Encounter Test Architect's methodology is based on test infrastructure compilation. Test engineers use the product's unified environment to specify, compile and verify full-chip test capabilities, including the individual test structures and the hierarchical (or flat) test infrastructure.
The Encounter Test Architect infrastructure compiler includes a new robust memory BIST capability with high fault coverage, easy BIST engine sharing, and automatic insertion and connection across the design hierarchy. Encounter Test Architect will be available for shipment at the end of April 2005.
An interesting new company, DeFacTo Technologies, is making its debut at DATE with technologies intended to effectively raise the level of abstraction for design-for-test (DFT) technology. With traditional DFT implementations confined to the structural level, they come late in the design process, and therefore are disconnected from main design decisions. The chip design flow has three major levels of abstraction: register transfer (RT) level (RTL), gates, and layout. DFT insertion is a design step on which other design steps depend. Until now, DFT implementations have been stuck at the post-synthesis gate level.
When ready for market, DeFacTo's tools will include solutions for scan insertion and built-in self-test (BIST) at RTL. DeFacTo's tools will fit non-intrusively into existing integrated circuit design flows, and will be used in parallel with other tools such as automatic test-pattern generation and additional complementary DFT tools. The DeFacTo tools will accept the same synthesizable RTL designs as those accepted by Synopsys' Design Compiler and other industry-standard logic synthesis tools.
Apache Design Solutions|
Cadence Design Systems
VaST Systems Technology