MUNICH, March 9 — Some readers may think that the life of an editor at an EDA industry event like DATE is all fun and games. You may envision editors doing things like eating rich traditional Bavarian food, or enjoying some of the social events associated with the conference, or experiencing the sights and sounds of a classic and beautiful European capital city. You might even be tempted to think that we'd go so far as to play with some of the neat (if somewhat geeky) technology demonstrations scattered around the show floor, like the fun "virtual baseball" demo found at Tensilica's booth.
Of course, you'd be right on all counts. But that's not what's at issue here. Your humble scribe willingly endured all of the above—arduous though it may be—to bring you the latest news from here at DATE, fresh as your morning coffee. And here's what caught my attention on this, the second day of the three-day exhibition.
Return of the Bride of ESL
There's no denying that electronic system-level (ESL) design is a central theme of DATE this year, and, looking ahead to June and the Design Automation Conference (DAC), it should be then as well. ESL news is rampant here in Munich this week. For its part, Manchester, U.K.-based SpiraTech has announced an OEM agreement with Novas. SpiraTech markets mixed-abstraction verification technology, and they've agreed to supply transaction capture and generation technology to Novas for its recently announced nESL system-level debug tool.
"More and more, verification means mixed abstraction," says Simon Calder, SpiraTech's CEO. In its collaboration with Novas, SpiraTech has helped craft a transaction-based debug environment that automatically extracts transaction information that inherently exists within system and hardware design and verification environments. Transactions are then displayed both graphically and textually within the Novas nESL environment for debug and analysis.
The integration of SpiraTech's Cohesive transaction tool wih Novas's debug technology will allow designers to analyze cause-and-effect behaviors or ESL or RTL designs for a wide range of standard protocols—without the costly and time-consuming effort of creating their own transaction extractors.
SpiraTech's Cohesive technology will be packaged as the nTE (Transaction Extractor) option for Novas's nESL debug environment. List prices start at $2500 for a one-year license and include a library of 10 adaptors including AMBA AHB and AXI, PCI Express and OCP-IP.
Speaking of OCP-IP, part of why ESL tools and methodologies are of such interest, especially among SoC designers, is that SoC design is really settling into a platform-based paradigm. Increasingly, SoCs consist primarily of an ARM or MIPS core, a standard bus protocol and a collection of garden-variety peripherals. The way in which SoCs ultimately distinguish themselves from one another is through software content. Consequently, design teams want and need plug-and-play functionality between IP blocks, both for the sake of easier integration and for the quickest possible verification of their communication amongst themselves. Where they really want to spend their effort is on the software side, not in trying to coerce disparate IP blocks into playing nice with each other.
The Open Core Protocol International Partnership (OCP-IP) is an organization that's spent the past few years looking to solidify support for the Open Core Protocol, an open standard protocol for creating communication sockets for IP blocks. OCP has indeed seen growing acceptance among designers in large OEM firms such as TI, Nokia, ST Microelectronics and Toshiba (all Governing Steering Committee members). OCP-IP has had a substantial presence at DATE in terms of its participation in IP/SoC-related panels and sessions. It also came to the show to announce availability of the new OCP 2.1 specification at the end of Q1.
The specification will now include profiles for the most commonly coupled OCP features and an advanced tagging scheme for enhancements in out-of-order processing. Profiles speed the designer learning processes by recommending sets of OCP features (with the associated configuration options) that are usually combined to solve typical design challenges. Also, tagging provides the ability for interconnect and targets in re-ordering transactions to non-conflicting memory addresses within a single thread. Unlike threads, which enforce no ordering restrictions, tagged transactions ensure that read/write hazards are respected by the system. Tagged transactions are particularly attractive for advanced embedded CPU architectures, like the MIPS 24K, which can exploit the parallelism offered by out-of-order transaction processing, but which require consistent memory ordering.
The OCP 2.1 specification will be available at the organization's website.
Goodbye Blue Monday
EDA tools are supposed to automate tedious drudgery, and sometimes they even succeed in doing so. Many designers have had the joy of manually entering Synopsys design-constraint (SDC) files for purposes of generating completeness and accuracy statistics. In release 2.1 of Silicon Dimensions' Chip2Nite tool for gate-level logic design closure, SDC files are automatically read and checked, allowing logic designers to verify the files early in the design process. This can save weeks of precious time and, at the same time, eliminate a pervasive source of design errors.
Silicon Dimensions also expanded the Chip2Nite Design Rule Checking (DRC) suite according to customer feedback making design analysis even more accurate. Chip2Nite, a suite of tools for floorplanning, seed placement, and analysis, includes auto-macro placement and block floorplanning capability.
Chip2Nite 2.1 also features new support for groups and regions, allowing designers to specify logic into groups and assign to specific regions of the floorplan; new post-placement analysis features, such as pin density, to reduce congestion; and support for top-level pins. The new version also sports 5-10X improvement in typical database load times, critical to performing rapid prototyping and what-if analysis. The additions and enhancements eliminate costly iterations between logic design and physical design reducing the overall design time by at least 20%.
Best of Both Worlds
Not everyone at DATE is strictly EDA in the classic definition. The French vendor of IP for reconfigurable semiconductors, M2000, unveiled a new architecture for its FlexEOS range of embedded FPGA (eFPGA) macros. Called FlexEOS-DSP, the architecture optimizes the performance and minimizes silicon utilization when implementing DSP applications in M2000's eFPGAs.
EFPGAs are SRAM-based and can be dynamically reconfigured to change the functionality of ASIC and SoC circuits after silicon processing and packaging. Doing so is as simple as downloading a bitstream to the reconfigurable logic.
The optional DSP-dedicated blocks offer a variety of operating modes: signed/unsigned multiplication, multiply-accumulation, multiply-addition and multiply-subtraction. Along with this comes configurable rounding and saturation for performance, which is also enhanced with pipeline registers. Memory blocks can be configured as four, eight or 16 bits, and have dual ports, which can be configured independently.
Each macro is delivered with a comprehensive software tool suite for compilation of the applications to be run on the macros.
Open Core Protocol International Partnership