Electronic Design

Drive Multiple Displays With A Single Microcontroller Port Line

Seven-segment displays are needed in many instrument designs. In conventional microcontroller-based designs, four output port lines are allocated for one seven-segment display. Figure 1 shows the conventional design for four seven-segment LED displays. In this case, two eight-bit output ports are needed for four seven-segment displays. Figure 2 shows another popular display-multiplexing design in which one-and-a-half eight-bit port lines drive four seven-segment displays. Because of the persistence of vision, the display has to be refreshed often to appear steady.

Figure 3 obviates the requirement of multiple port lines. Here, four displays are driven through one port line. (Theoretically, any number of displays can be driven through one port line by this method.) The port-line output should be a pulse train generated through software, whenever the display needs to be updated. The first pulse should be a long pulse and the subsequent pulses are a number of short pulses the number being equal to the number that will be displayed.

The IC1 monostable and AND gate act as a long-pulse detector. IC2 to IC5 (CD40110) are decade up-down counter/latch/display drivers. The microcontroller should generate a pulse with a duration that s longer than the time delay generated by the retriggerable monostable multivibrator. The Q output of the monostable circuit is ANDed with the pulse input.

During the long pulse, the AND gate output goes High for a duration that s longer than the monostable delay. This output resets all of the counters to zero.

Other pulses whose widths are less than the monostable delay won't produce a High output at the AND gate. Thus, the long pulse alone clears the display. Subsequent pulses shorter than the monostate delay time, whose number is equal to the four-digit number to be displayed, will be counted by IC2 to IC5 and then drive the displays. Typical values for long-pulse duration can be 5 ms.

The monostable delay is 1 ms, and the pulse train has 2- s ON and 2-┬Ás OFF times. For these typical values, the display gets updated within 45 ms for the maximum display of 9999. Unlike the multiplexed display scheme shown in Figure 2, the display needn't be refreshed continuously. The next display can be loaded after one second, or as needed.

Such a scheme will be quite useful when designing compact systems that have microcontrollers with fewer output pins. This technique will also be handy for adding displays to already manufactured equipment at a later date, since only one port line is needed. If two port lines can be made available, the circuit can be simplified by eliminating the long-pulse detector circuit that uses IC1 and the NAND gate. One port-line output can be used to clear the counter/ display, and the pulse train can be sent on the other port line.

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