Electronic Design

Embedded Processor Directly Drives An On-Screen Display

Visualization of measurement results or application status is an increasingly requested feature. However, the generation of images on a TV screen does not always require expensive cards or chips. In some cases, a black-and-white picture will suffice.

The black-and-white video signal accepted by standard TV equipment requires only three discrete voltage levels. This signal can be further separated into two binary components: the synchronization signal and the picture signal. This property can be utilized advantageously during video-signal synthesis. The synchronization signal is always the same. Only the picture component differs from image to image.

The synchronization signal can easily be generated by an intelligent timer peripheral, according to a static lookup table. A suitable timer peripheral is often present on-chip in modern microcontrollers or DSPs.

The on-screen display (OSD) is formed by a picture data stream consisting of pixel values (black = 0, white = 1). The simplest way to generate such a data stream is to make use of al-most any serial on-chip interface, such as a synchronous serial port or an SPI peripheral. This interface simply transmits data from a pixel map stored in memory. This operation must be aligned with the synchronization signal generated by the timer. This requirement can easily be met by taking advantage of the timer-interrupt feature.

The above idea was tested using the DSP56F805 from Motorola. The im-plementation of the OSD circuit is shown in Figure 1. The circuitry needed to convert the two digital signals into an analog-video signal and the output amplifier needed to match the 75-Ω input impedance of the TV set can be arranged in a configuration as simple as that shown in Figure 2.

When considering image quality, a compromise must be made between resolution and the memory space needed for the picture pixel map. The required computing power increases with picture resolution. More performance is required than the raw power needed to actually display the picture—the creation of the picture in memory can be even more demanding than displaying the image itself.

In this application, the compromise between resolution and memory space resulted in a resolution of 256 by 287 pixels with about 20% of the computing power consumed by the display process. The maximum reasonable resolution achievable with this particular DSP would be about 1024 by 574 pixels. Note that while the horizontal resolution can be freely modified, the vertical resolution is defined by the appropriate video standard (a PAL-compatible TV set was used in this case). An example of the displayed picture is shown in Figure 3.

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