Layout for ICs at process geometries of 90 nm and below becomes a very dicey affair. Even at 180 nm, the number of design rules that must be enforced for an ASIC or system-on-a-chip to be manufacturable are exploding. At 90 nm, the interdependency between upwards of 2000 rules is such that they become a tangled rat's nest that's impossible to manage without automation.
Clearly, designers need layout tools that mind design rules. That's what BindKey Technologies achieved in its RapiDesign-Clean rules-driven layout package. Not only does RapiDesign-Clean check to ensure that layout edits are within rule boundaries, it also shows designers where to place structures within the layout without creating rule violations. Unlike tools that check for such violations after the layout's been completed, RapiDesignClean checks for rule compliance in real time during the layout process.
Working in tandem with Cadence's popular Virtuoso layout editor and the user's DRC signoff tool of choice, RapiDesignClean applies all design rules with virtually no delay. It provides visual feedback of applicable rules at each edit in less than one second.
The tool displays rules as visible "hints" on the layout editor screen, immediately notifying designers when a violation is created. It remains aware of all rule occurrences in the vicinity of any individual edit made to a given layout, from start to finish of a layout editing session. Importantly for nanometer designs, the tool handles all rules that involve complex operations on a combination of metal layers.
RapiDesignClean imports the design rule deck directly from the layout editor and from industry-standard design rule tool formats. It supports design rules for technologies at 180 nm, 130 nm, 90 nm, and smaller for both analog and digital, bipolar or CMOS.
The RapiDesignClean rules-driven layout tool is available now with pricing starting at $15,000. It's offered for Sun Solaris UNIX-based platforms now with a port to Linux coming this summer.
BindKey Technologies Inc.