Electronic Design

IDE Lays SystemC Designs Bare For Easier Debugging

Sometimes design abstraction is a help, and sometimes it's a hindrance. Verification of system-on-a-chip designs with SystemC has a demonstrated ability to significantly speed up simulation runs. However, analysis and debugging at abstraction levels higher than cycle-accurate have proved difficult and time-consuming.

Summit Design's Vista 1.1, an integrated development environment (IDE) for SystemC-based analysis and debug, is equipped with a transaction-level modeling (TLM) viewer that works with the user's SystemC simulator (see the figure). What you get is direct observability of the key attributes of SystemC transaction-level models, including time, kernel cycles, return value, function attributes, structure, and concurrency.

Users can automatically view communication protocols and system-level interfaces, with a view of transaction function calls between blocks. There's no need for the time-consuming manual code instrumentation that's historically been necessary in SystemC debug environments, either.

Vista's TLM waveform viewer expands simulation time to display simulation cycles, allowing users to clearly view the event ordering that's critical to the debug of event-based and untimed designs. Vista efficiently handles SystemC instance-specific breakpoints. The waveform viewer displays not only system-specific signals, but also any object in the design.

Vista is suitable for both experienced and novice SystemC designers. With the tight link between the IDE's design and code browsers, new SystemC users can easily understand a design. Vista 1.1 will be available in the third quarter for the Linux platform. Prices start at $5000 for a one-year license.

Summit Design Inc.

TAGS: Components
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