Processing And Material Advances Steal The Spotlight At IEDM

Next week’s 51st IEEE International Electron Devices Meeting in Washington, D.C., provided a glimpse into the future of IC technology. Invited presentations from STMicroelectronics, Stanford University, and Toshiba Corp. are scheduled to open the conferen

Dave Bursky

Nov. 28, 2005

2 min read

Next week’s 51st IEEE International Electron Devices Meeting in Washington, D.C., will provide a glimpse into the future of IC technology. Invited presentations from STMicroelectronics, Stanford University, and Toshiba Corp. are scheduled to open the conference by examining microelectromechanical systems (MEMS); the scaling, power, and future of CMOS; and the past and future of information displays, respectively. Also, the wide range of presentations will cover many aspects of fabrication.

The show will include several key highlights:

Session 5 will reveal a flexible, lightweight Braille sheet with plastic actuators driven by an organic FET active matrix developed by the University of Tokyo and the National Institute of Advanced Industrial Science and Technology in Osaka, Japan.

Researchers from Princeton University will detail an approach to implementing thin-film transistors on stretchable elastomeric substrates. Potential applications range from prosthetic skin to sensor arrays that can be stretched over a surface.

New memory concepts like nanocrystal-based devices, non-volatile devices that employ a solid electrolyte, and carbon nanotubes used as mechanical switches also are planned as major topics of discussion.

Session 7 will cover advances in MONOS (metal-gate oxide-nitride-oxide) and nanocrystal-based memories.

Session 19 will showcase Sony’s novel approach to magnetic non-volatile memory using electron spin torque switching as well as a nanoelectromechanical FET from U.C. Berkeley that can serve as a storage device.

Session 31 will illustrate emerging resistive switching technologies based on phase-change memory arrays and the use of metal-insulator-metal structures.

Session 35 is scheduled to cover developments in NOR flash technology as well as in ferroelectric, magetoresistive, and phase-change memories.

Toshiba will highlight devices with features as small as 35 nm and employing double-junction tunneling, while Samsung will describe a multibit programming scheme for flash memories using a resonant tunnel barrier. These schemes reduce the voltage dispersion and allow the creation of memory cells that are more robust.

For more information, go to the IEEE International Electron Devices Meeting website at www.ieee.org/conference/iedm.

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.