Mentor Graphics is regarded as a market leader in at least two areas. One is in the deep back end of the IC production process, thanks to the company's Calibre suite of resolution-enhancement-technology (RET) tools. The other, paradoxically, is in the very front end. Mentor's Seamless hardware/software co-verification environment enjoys a commanding market share.
In spite of Seamless' entrenched position, Mentor rolled out a new version that extends and deepens its capabilities beyond finding bugs. No longer content to answer questions about whether hardware and software will work together, Version 5 of Seamless explores how well hardware and software will work together.
Seamless now can collect data on system performance and graphically depict where the performance bottlenecks exist. Working from a hardware description in either Verilog, VHDL, or SystemC, Seamless performs a number of analyses that can show where the holes are in a system design.
First, the tool performs code profiling. It identifies the software modules that consume the most CPU time. Because the tool performs detailed hardware simulation (depending on the models' detail), it can determine how many CPU cycles are being used by any and all software modules.
Also, memory transactions (reads, writes, and cache hits and misses) are analyzed. It can tell designers whether caching algorithms need to be tuned or if larger caches are needed.
Another performance metric gauged by the tool is bus loading. The tool measures each software module's bus-bandwidth consumption. Armed with that data, it then can determine whether or not critical functions are getting the bandwidth they need.
Finally, Seamless now clocks bus waiting time. It displays how long each master waits for a bus grant, giving designers ammunition for adjusting bus arbitration schemes and priorities.
Version 5 of the Seamless co-verification tool starts at $40,000 (depending on feature set) for a perpetual license.
Mentor Graphics Corp.
www.mentor.com
