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Electronic Design

SiP Really Packs It In

System-in-a-package technology fulfills the need for high-density, small-footprint products with short turnaround times by using low-cost, standard assembly equipment.

Shorter development times and and cost-effective miniaturization make for an unbeatable combination. Those just happen to be the attributes of the quickly rising system-in-a-package (SiP) technology. In a straightforward manner, SiPs can also integrate a number of heterogeneous technologies—for example, a variety of silicon ICs and discrete components—in a minimal footprint.

Present SiPs can incorporate microprocessors, memories (like EPROMs and DRAMs), FPGAs, resistors, capacitors, and inductors in a package that holds up to four or five die. Several companies leading the pack in developing SiP solutions aren't just coming up with their own approaches, though. They're also working with leading IC chip manufacturers on novel SiP solutions (see "A Rosy Outlook For SiP Technology," p. 50).

To a large extent, SiP technology has stepped in to fill the void left by system-on-a-chip (SoC) technology's higher development and non-return engineering (NRE) costs and longer time-to-market. New SoCs require significant investments in time and money, something that many products (particularly those on the consumer end) can't afford.

For instance, some SoCs can take 18 months to reach the market, while SiPs can cut that time by 50% or more. With their vertical integration, SiPs can shorten interconnect distances as well. This reduces signal delay times, noise, and capacitance effects, allowing higher signal speeds. Power dissipation is lower too.

In some cases, SiPs serve as an interim step for further SoC development that will eventually merge everything onto one silicon chip. This is particularly true in Bluetooth devices, cell phones, automotive electronics, imaging and display products, digital cameras, and power supplies.

SiPs have adapted well to the packaging needs of these applications, often slashing real-estate area by up to 80% and weights by 90% compared to conventional IC packages. One key reason behind those numbers is the use of surface-mount technology (SMT). SiP technology blends the SMT of electronic manufacturing services (EMS) with those of semiconductor assembly services (SAS).

SiPs started out by stacking memory and logic chips together for many consumer applications. In fact, Intel recently developed a folded-stack chip-scale package (CSP) SiP with logic and memory (Fig. 1). In 1998, Sharp Corp. introduced the first stacked chip-scale package consisting of bare die flash memory and SRAMs for use in cellular phones.

Many other companies followed suit. Valtronic SA uses the folded concept to combine logic, memory, and passive components into a single SiP for use in hearing aids and heart pacemakers (Fig. 2). Now, companies are trying to add microprocessors, power devices, passives, and other functional components.

The folded-stack CSP in use by many companies uses Tessera's patented 3D mZ fold-over ball stack concept, which the company pioneered in the mid-1990s, for high-reliability applications. The concept allows up to eight DRAM, SRAM, or flash memory chips to be stacked into a multichip assembly. It uses a flat, flexible polyimide tape that's attached to a chip die and then folded over for interconnecting the next stacked die on top.

The convergence of video, audio, and data is a large driving force for using the SiP concept. "The integration of data, voice, and video in smart phones and PDAs requires higher performance, longer battery life, and increasing memory density in a sleek package," says Hyung Lae Ruh, executive vice president for Samsung's R&D Center. "Our SiP solution offers the first combination of an application processor with NAND flash memory."

SiP solutions come in various shapes: stacked-chip structures that target small form-factor needs; side-by-side solutions for I/O terminal functions; chip-on-chip (CoC) form factors for high-frequency and low-power operation; multichip modules (MCMs) for higher packing densities; and chip-on-board (CoB) structures for large memory devices. In many of these form factors, chips and other components are integrated vertically within a small footprint. Often, SiP is referred to as 3D packaging.

In fact, third-dimensional (vertical or z axis) manufacture of IC chips is an ongoing R&D effort with its own successes. This shouldn't be confused with 3D packages that put different functions (memory, logic, CPUs) on different chips and then stack them together in one package.

Instead, SiP packaging takes advantage of much shorter chip interconnect lead lengths. This is the same goal for 3D silicon ICs, because increasingly complex ICs have become more difficult to connect to one another.

A key development in SiP technology is the introduction of SiliconPipe's Off-The-Top (OTT) technology. The concept enables high-speed (more than 20 Gbits/s over a distance of 3 in.) signals to transmit off the top of one package on a uniform impedance-matched transmission line to the top of another package. Such a concept could ultimately push designers toward an SiP approach instead of an SoC design (Fig. 3).

According to Mark Bird, senior director of technical marketing for Amkor, and Joseph Adam, vice president for strategic marketing at Skyworks Solutions Inc., the most common types of SiP packages are stacked-die packages, stacked packages (package atop a package), and modules (Fig. 4). Laminate-substrate SiPs are the most dominant, with ceramic, lead-frame, and tape substrate use on the rise.

Amkor employs the SiP concept for digital cameras, where it uses laminate substrates that are built in matrix strips. A flexible circuit contains components and a connector as well as a pc-board-mounted image sensor. On top of all this sits a module that houses the camera's barrel, lens, infrared glass, mount, and adhesives (Fig. 5). According to Amkor, its approach follows standard handling and permits the use of standard equipment, thus lowering costs.

SoCs typically have a tough time meeting market demands when integrating digital computational electronics with power and RF ICs. Often, designers need to wrangle with devices made on different processing platforms, such as bipolar, gallium arsenide (GaAs), and silicon germanium (SiGe)—not just CMOS.

"It is very difficult to integrate these diverse technologies in one silicon package," explains Don Desbians, executive vice president of technology for Fairchild Semiconductor. "We're heavily involved in SiP technology for power products that serve a wide range of applications from a couple hundred watts to 1 kW. Our European customers are demanding power-efficient products for consumer applications like home heating, which we supply in Smart Power modules (Fig. 6). The automotive sector offers additional SiP power applications, with multidie quad flat no-lead (QFN) packages for highly inductive loads."

Skilled RF designers are a very valuable commodity, particularly in packaging RF products. Here, a certain "black magic" is needed to get the design right. It's not surprising, then, that designers of complex RF circuits turn to SiP technology, which has proven cost-effective by isolating yield issues. That's because the RF circuit may be on one substrate while other electronics within the SiP reside on another.

Skyworks Solutions, one of the largest and most successful companies providing RF SiP products, offers direct quadrature modulators in SiPs for RF communications applications. For example, there's its land-grid-array (LGA) fully integrated GSM/GPRS radio in a single package. As small as a U.S. dime, it shrinks radio size by more than two-thirds for cellular applications (Fig. 7).

Anadigics has come up with a novel SiP scenario that integrates RF ICs, a power amplifier, a switch, and other related electronics with a heatsink, microprocessor/controller, capacitors, inductors, and filters into a single module (Fig. 8). The company claims that its approach is more cost-effective than an SoC design.

For medical electronics, another growth area, costs must be lowered and products must be simplified. This is crucial when attempting to boost the efficiency of surgical implants like pumps, hearing aids, and electro-neuro stimulation.

One soon-to-arrive product is Valtronic's Watch Communicator. Patients will use this small, universal, battery-operated programmer to control and monitor implanted and non-implanted medical devices via an RF downlink transmitter and an RF uplink receiver.

Wafer thinning is a primary technical challenge to SiP growth. Today's automated wire-bonding equipment for 200- and 300-mm wafers can handle wafers as thin as 50 µm, allowing for dense wafer stacking. Anything much thinner, though, turns into a problem for automated equipment. Wafers become too fragile, leading to more frequent breakage. And, electrical "punch-through" effects from wafer to wafer can ruin a chip's performance. Standard wafer thinning for ICs typically measures 175 mm.

Another challenge is the need for proper computer-aided-design (CAD) tools to maximize electrical, mechanical, and thermal designs in a multifunctional concurrent-design environment, according to David B. Tuckerman, senior vice president and the chief technology officer for Tessera Inc.

At Tessera's recent 2004 System in a Package Symposium, Tuckerman explained that "optimization of packaging and interconnects is a critical design process." He went on to say that functional silicon takes up approximately 1 in.3 in a rack full of electronic equipment. Packaging and interconnects take up most of the rest of the space.

Heat paths at the system level must be better understood as SiP packages get denser and smaller. "We need system-level thermal CAD models," Tuckerman said.

He also noted that the availability and cost of tested die, whether bare or packaged, is a large business challenge when stacking mixed types of devices in an SiP. The management of die supply, test and burn in, and yield are all important issues in a supply chain. Tuckerman pointed out that a packaging company is often in the best position to coordinate how this chain will function.

Putting the right assembly equipment in place throws up another roadblock in SiP growth. The 2004 National Electronics Manufacturing Initiative's (NEMI's) SiP roadmap calls for future placement equipment that can handle die placements from wafer formats with 15-µm accuracy at less than $0.005 per placement. However, at this point, industry can't meet such a goal with current assembly equipment. The SiP packaging industry is working on this problem.

Another challenge is merging the business models of the EMS and SAS sectors with regards to profit margins. The SAS sector generally expects higher profit margins than the EMS sector because it uses standard manufacturing environments. The former group must consider a larger overhead, though, due to the need for clean rooms, as well as R&D expenses.

STATSChipPac, which merged with ST Assembly Services, believes it has positioned itself to fulfill many of the aforementioned challenges. The company is a major SiP manufacturer.

The path for SIP technology reveals that more and more semiconductor die and packages will be stacked on top of each other for deeper 3D packaging. Fujitsu already produces an eight-chip stack SiP that combines existing multichip packages in one stack (Fig. 9).

Advanced Semiconductor Engineering (ASE) Inc., one of the first companies to achieve volume production of SiP technology using chip-scale packaging and stacked-die packages, foresees its own SiPs with eight-die stacks and five-package stacks by next year. That's roughly double what was achieved last year. ASE, with its expertise in mass production of 300-mm wafer flip-chip bumping, assembly, and test services, recently announced a joint strategic partnership with NEC Electronics Corp. in which ASE acquired NEC's packaging and testing operations.

Tessera foresees system-level integration for SiPs, leading to dense, highly integrated computational modules with different memory types, ASICs, and a microprocessor. Each would be packaged in its own flip-chip assembly (Fig. 10). Eventually, SoC technologies may mature enough to integrate the same components that can't be integrated cost-effectively on the same silicon substrate: antennas, crystals, filters, shields, and other passive components. For now, though, several generations of SiPs with higher integration levels must be developed before this becomes a reality.

Looking further ahead, SoCs may not be the final packaging answer. We may yet see the emergence of interconnects via light, RF, and microwave rays, or possibly even nanotubes, spin-coupling, and molecular interconnects. In these cases, the need for packaging is greatly reduced if not altogether eliminated.

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