SoC Error Protection Passes Sparc Test

A technology for embedding error-protection intellectual property (IP) within systems-on-a-chip (SoCs) without significantly degrading performance has proved itself. Santa Clara-based iRoC Technologies Corp. has shown that its error-protection IP adds no delay in a Sparc 32-bit V8 VHDL core's memory and logic circuits compared to an implementation of the same chip without the IP.

IRoC's embedded Robustness IP blocks track soft errors in processors. The Sparc V8 core used in the tests was upgraded for protection against transient faults in memories and logic blocks. The embedded IP provides self-correcting intelligence for observing signals at two different instances and comparing the instances to filter out transient phenomena (see the figure).

The resulting robust netlist was manufactured using a commercial 0.25-µm process. The silicon was stressed under radiation attack at a cyclotron facility in Belgium to simulate soft errors. A nonprotected implementation of the original Sparc chip was similarly tested.

Silicon results proved the Robustness IP did not strap SoC performance as simulation tended to show. The blocks in memory and logic added no extra delay compared to the die based on the original netlist. And while the original die displayed soft errors, no such errors were observed in the robust Sparc chip.

For details, visit www.iroctech.com.