In separate integration efforts, Tool Corporation, the Japan-based provider of the Lavis layout-visualization platform, is looking to address design-for-manufacturing issues as well as physical verification and debug issues. Tool Corp. has worked with Brion Technologies on an environment for DFM and with Magma Design Automation on the physical-verification front.
Tool Corp. and Brion have built an integrated IC design environment that incorporates Tool's Lavis platform and Brion's OPC and RET/OPC verification system, Tachyon. The integrated environment is aimed at semiconductor fabs, photomask shops and fabless IC design houses that pursue design for manufacturing (DFM) flows now and in the future. Tool and Brion have combined Lavis' large-volume data handling and high-speed data display capabilities — which can utilize all the data formats used throughout the chip design processes — with Tachyon, a computational lithography platform that can execute high-speed, full chip simulation and inspection with high precision.
This integrated environment can first display chip design data with Lavis, conduct lithography simulation of designated areas of that design within Tachyon, and then display the results again with Lavis. Because design data and simulation parameters are seamlessly and automatically communicated between Lavis and Tachyon, the user is able to easily obtain simulation results without difficult and complex data preparation.
As chip geometry continues to shrink from 65 nm to 45 nm and then 32 nm, device patterns are becoming more complex because of the optical-proximity correction (OPC) used to ensure that sub-wavelength features in these patterns are transferred correctly onto silicon. To achieve accurate OPC, it is critically important for high-speed, accurate simulation to verify design data and OPC data during the design process, which is provided by Brion's Tachyon.
But the complex, aggressive OPC patterns being incorporated into today's leading-edge designs can result in skyrocketing increases in the data volumes of these designs. In the past this has made data handling extremely difficult and time consuming. However, the integration of Tool and Brion's platforms together enables repeated high-speed simulations and verifications to address hot spots and parameter alterations, as well as data modifications, thanks to Lavis' partial editing capability, bringing about substantial improvement of design verification turn-around time.
In a separate development project, Tool Corp. has integrated the Lavis platform with Magma Design Automation's Quartz DRC (design-rule checking) and Quartz LVS (layout-vs.-schematic) physical verification tools. A streamlined graphical user interface (GUI) enables the combination to hasten physical verification and debug.
Quartz DRC and Quartz LVS provide fully scalable physical verification with distributed processing, enabling physical verification of entire multimillion-gate chips in two hours, Magma claims. Lavis, capable of handling very large designs, provides an exceptionally fast visual platform for reviewing verification results. Identified errors can be organized into cell or error type, allowing users to debug them sequentially by viewing them quickly and conveniently on Lavis. There is no need to wait until DRC jobs complete. Moreover, since Lavis allows editing a small portion of a large amount of data, users can also fix errors while checking identified errors in the same environment.