Electronic Design

True-3D Chip-Layout Editor Facilitates Stacking Of Disparate Wafers

Say you wanted to create a chip in which a processor fabricated in 32-nm process rules would be combined with memory done on a 65-nm process and analog blocks fabricated at 180 nm. This leads you to consider chip/wafer-stacking technologies, most of which are out of the question for existing layout editors.

A favored technique for chip stacking, known as through-silicon via wafer stacking, allows distinct wafers to be stacked on each other and connected internally. This results in chips with denser designs and higher performance.

According to Micro Magic, its MAX-3D is the industry's first true 3D-aware layout editor as well as the only commercially available editor capable of supporting through-silicon via wafer stacking. MAX-3D can combine distinct process wafers while allowing the designer to view, edit, and connect the independent wafers into one 3D stacked chip.

Moreover, no changes need to be made to the foundry-supplied process design kits (PDKs) to incorporate these technologies in MAX-3D. It manages multiple levels and their respective tech files independently and collectively. Other capabilities include connectivity tracing, design-rule checking, and many other features found in the company's earlier MAX layout editor. It also offers a direct interface to Calibre and Calibre RVE.

MAX-3D has been demonstrated to display and edit a design of 1.2 trillion devices in real time. It's fully programmable and customizable, and it integrates well with other EDA tools. It's now available for a 30-day trial to qualified IC design organizations.

With MAX-3D, wafer levels can be edited separately, or concurrently without writing a new tech file. Tech files for each wafer level are maintained individually, and you can edit technologies for different wafer levels in the same view.

Contact Micro Magic directly for pricing information. Micro Magic Inc. www.micromagic.com/max-3d.html

TAGS: Components
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