Electronic Design

Upgrade Gives FPGA Design Environment 60% Boost

With more ASIC developers moving to large complex FPGAs, FPGA design flows must include ASIC-like features like floorplanning and optimized synthesis. Of course, FPGA designers require software tools tailored to specific architectures, and users of Actel's ProASIC Plus devices are no exception.

With enhanced synthesis and place-and-route tools, version 5.0 of Actel's Libero integrated design environment (IDE) delivers a performance gain of more than 60% for the ProASIC Plus FPGAs. Actel's Designer v5.0, the physical design tool suite within the Libero IDE, delivers a comprehensive user-driven floorplanner and a powerful graphic interface.

Also included within Libero are expanded interfaces to external tools, such as Mentor Graphics' Precision and LeonardoSpectrum synthesis tools, Synplicity's Synplify Pro synthesis tool, and Actel's own programming and debugging tools.

The environment features Synplicity's Synplify 7.3 software, which has been enhanced for improved quality of results for Actel's FPGAs. Also featured are SynaptiCAD's WaveFormer Lite v9.0 and Mentor's ModelSim v.5.7.

The ChipPlanner floorplanner lets designers achieve optimal tradeoffs between design density and performance by managing regions, logic placement, I/O assignment, and routing. Also new is the Multi-View Navigator, a graphical interface that provides simultaneous displays of the floorplanner, netlist, package, I/O attributes, hierarchy, and log window.

The suite manages all design and report files, seamlessly passing data between tools. It supports mixed-mode design entry, giving designers the choice of mixing Verilog or VHDL blocks with schematic modules in a design.

Libero IDE v5.0 comes in Silver, Gold, and Platinum versions. Silver and Platinum evaluation editions are free via Actel's Web site. Pricing for the IDE starts at $595. The Platinum version starts at $995.

Actel Corp.

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