Nowhere has algorithmic synthesis been more popular than with DSP designers. Until now, algorithmic synthesis has concerned itself largely with microarchitectures, allowing DSP designers to trade off and explore various combinations of adders, subtractors, multipliers, and other functions to determine the best implementation for their designs.
With the latest revision of its algorithmic synthesis tool, AccelChip takes the next step with macroarchitectural exploration. Thanks to AccelChip's "IP-Explorer" technology, its DSP Synthesis 2005.4 can automatically select and insert an optimal DSP IP implementation from within the company's AccelWare libraries. This is done for each function within the design-based frequency, throughput, bit width, area, sampling rate, and other requirements.
Consider a fast Fourier transform (FFT). In macroarchitecture terms, the designer must trade off between an array of options. Now, the tool will account for parameters like the number of radixes, the type of FFT, its bit length, whether its input is array or scalar, and whether the data input is real or complex.
Once the macroarchitecture is selected, the tool will choose the best IP core for the application at hand based on design constraints. The original Matlab code is maintained as a golden source. Users can override the tool's choice if they desire. The company has recently expanded its offering of linear algebra IP generators.
Version 2005.4 of AccelChip DSP Synthesis with IP-Explorer is now shipping, as are the current versions of the AccelWare IP Generator Toolkits. Current customers on support will receive the release at no charge. Otherwise, contact AccelChip for pricing.