Two ARM cores, the ARM 9E from ARM Ltd. and the pT-120 ARM 4T from picoTurbo Inc., were an-nounced at October's Microprocessor Forum 2000. These ARM devices incorporate direct Java bytecode execution and new single-instruction/multiple-data (SIMD) instructions.
While the ARM 9E's improvements are relatively independent, the changes illustrate how the existing processor core can be used for additional functionality. The SIMD enhancements target multimedia and signal-processing applications. They ideally complement the 32-bit RISC architecture since the SIMD processing addresses 8- and 16-bit data. The SIMD instructions use the existing register file and an enhanced arithmetic unit, and the ARM Java support employs the ARM register file for Java registers.
The Java virtual machine (JVM) is invoked by a new instruction, BXJ. It enables an instruction front-end processing unit that converts incoming bytecodes to ARM instructions, which are executed by the core processor. Simple Java bytecodes such as add or subtract are converted into one ARM instruction. More-complex bytecodes like floating-point instructions and creation of a new Java object are converted into a call to support code that implements the matching part of the Java virtual machine.
Java support uses the first four registers in the register file as a Java expression stack cache. Compared to a Java software implementation, the hardware implementation greatly improves the execution performance. Java execution streams can be interrupted, just like normal ARM instruction streams. Similarly, software exceptions will exit the Java execution state and start executing a native code-exception handler. Using minimal power, the Java support requires only an additional 12 kgates. The JVM support also is half of what a typical software implementation requires.
ARM's implementation is impressive but not unique. JSTAR from Nazomi Communications, formerly Jedi Technologies, is similar. The JSTAR IP is available for a variety of microprocessor cores, including ARM. As with the ARM implementation, no just-in-time (JIT) compiler is necessary.
The pT-120 ARM 4T core operates at the low power levels required by 3G wireless devices. It can execute Java applications using a software-based JVM and JIT. But its IP is configured for lower-power operation while still providing high performance. The independent data and code caches can be 0 to 64 kbytes. Also, the pT-120 supports DSP extensions and fast context switching. It can operate at speeds up to 500 MHz. And, the core only needs 2.1 mm2 of area when made on a 0.18-µm process.
For more details, point your browser to www.arm.com, www.jeditech.com, and www.picoturbo.com.