The wide range of oddball frequencies required by communications equipment these days makes it tough for one IC to deliver even a few of them. Yet Silicon Laboratories has figured out a way to generate almost any desired output frequency for networking, telecommunications, wireless basestations, test and measurement, HDTV video, and data acquisition.
The Si53xx series of clock-multiplier chips can generate any output frequency from 2 kHz to 1.4 GHz. The ultra-low jitter generation of the Si53xx synthesizers rivals traditional analog phase-locked loops (PLLs) built discretely using expensive voltage-controlled crystal oscillators (VCXOs) or voltage-controlled surface-acoustic-wave oscillators (VCSOs).
The Si53xx architecture is a phase-locked loop (PLL) multiplier with frequency dividers at the input and output and in the PLL feedback path (see the figure). By selecting the correct set of divider ratios, designers can achieve almost any desired output frequency.
At the heart of the design is Silicon Labs' DSPLL, which is a unique PLL with a DSP loop filter. This filter has selectable bandwidths that let engineers change the loop bandwidth without changing components as well as enable jitter performance optimization at the application level.
There are four clock inputs whose frequencies can be any source between 2 kHz and 710 MHz. There also are four differential clock outputs. Such flexibility eliminates the need for external multiplexers and clock distribution buffers.
Available now, there are nine different models in the Si53xx series. Prices range from $12.10 to $72.45 in 1000-unit lots.
Silicon Laboratories Inc.