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Electronic Design

Configurable DSP Core Offers Instruction Parallelism

Designers looking to incorporate embedded DSPs in their SoCs have at least three options. They could try a general-purpose fixed DSP even though it may not particularly suit their application. Or, they could opt for one of the application-oriented DSPs that have been appearing from the larger DSP vendors. A third solution, offered by a growing number of DSP IP vendors, would be a configurable DSP core that can be tailored to specific applications.

Falling into this third camp is Improv Systems Inc., Beverly, Mass. This company has rolled out its Jazz 2 configurable DSP architecture and accompanying tool suites. The second generation of Improv's Jazz DSP core is an attempt to broaden the core's appeal beyond high-end applications and into a wider range of embedded DSP uses.

In its initial incarnation, the Jazz architecture was only 32 bits. The Jazz 2 architecture also offers 16-bit support, broadening its potential application base. The VLIW processor can be implemented in as few as 50 kgates while drawing less than 0.5 mW/MHz. New power-management features let users selectively toggle sections of the processor on or off, enhancing its low power consumption.

Code density is likewise improved in the Jazz 2 architecture. Its two-stage compression scheme yields a 50% improvement over the earlier version by eliminating "no-ops" in the program memory image. Also, it provides for instruction overlay, letting users balance parallelism with code density. As a result, Improv claims, the Jazz 2 architecture offers code densities that are 50% more efficient than its predecessor and rival single-issue DSP architectures that don't offer instruction-level parallelism.

The architecture provides for designer-defined computation units (DDCUs), which are configured to extend additional parallel data paths (see the figure). On top of that, designers can configure parallel processors with shared memory access for further processing power. The architecture is seen as the beginnings of a "meta-platform" for an SoC design that's being extended by key IP partnerships for platform components, including microprocessors and on-chip buses (ARM, MIPS), memory subsystems (Denali), an RTOS (Wind River), and protocol signaling stacks (RadVision, HNS, and Jungo). Recently, an integrated development environment was announced for designing with Jazz cores and CPU cores from ARM.

A number of pre-designed versions of the Jazz core are available, from a single-MAC to dual- and quad-MAC types. A tool suite comes in two flavors, one for software design only and another for hardware/software codesign.

For details, call Improv at (978) 927-0555 or visit

TAGS: Digital ICs
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