Electronic Design

Configurable DSP Core Spurs 3G Wireless Baseband Architecture

To stay competitive in the burgeoning 3G wireless communications sector, which is projected to reach $9.2 billion by 2005, National Semiconductor Corp. has forged a technology partnership with 3DSP Corp., a maker of configurable DSP cores. Using 3DSP's SP-5 proprietary superscalar DSP core with single-instruction/multiple-data architecture, also known as SuperSIMD, National is prepping a configurable system-on-a-chip (SoC) for 3G cellular applications.

Besides the SP-5 core intellectual property (IP), National also will use 3DSP's HiFI design and development environment. To develop this next-generation baseband technology, National will combine the SP-5 core with other system-level IPs the company obtained by acquiring Algorex Inc. in December 1999. Algorex also will provide DSP algorithms and system-level design expertise.

"We are developing a new baseband architecture that requires a scalable and flexible DSP core that will meet the low power consumption and high data rate needs of 3G wireless connectivity," says William Stacy, vice president of the wireless product line at National Semiconductor. He adds that only a new approach to baseband architecture will address the stringent power and speed requirements of 3G cellular handset applications. In essence, this distributed processing architecture incorporates multiple DSP cores and a microcontroller, in addition to other IPs.

"The partnership with 3DSP provides National Semiconductor with a state-of-the-art DSP capability that will enable it to expand on its wireless experience to move quickly in producing 3G cellular products," says Will Strauss, president of Forward Concepts, a market research firm in Tempe, Ariz.

Scalability, configurability, and high performance motivated National to adopt the SP-5 DSP core in its new baseband architecture, notes Kan Lu, 3DSP's cofounder and chief technology officer. With a performance of 880 million MAC/s (MMACs) at a 220-MHz clock frequency, or 3.52 billion RISC-like operations per second (GOPs), the fixed-point SP-5 is a low-power cost-effective engine for most demanding DSP applications, he asserts. A highly flexible, integrated (HiFI) design environment supports it. Furthermore, Lu continues, this fully synthesizable DSP core can be easily ported to any process and library.

According to 3DSP, HiFI is a fully configurable high-performance DSP design platform. It lets designers configure the SuperSIMD DSP core to their specific needs, allowing them to specify the number and width of the multiplier, the register set, the memory banks, and other similar functions on the chip. Along with modifying the instruction set, HiFI permits users to add application-specific instructions. This unique feature ensures maximum DSP power, 3DSP says. In short, it is a completely integrated Web-based design environment that lets designers see results before committing to hardware.

Presently, National is porting the SP-5 DSP core to its CMOS ASIC library. Using a 0.18-µm CMOS process, the supplier expects to see the prototypes of its new baseband chip before the end of the year and hopes to supply it to key customers by early next year. For volume production, National is planing to migrate to 0.15-µm design features.

Meanwhile, 3DSP is readying a version of SP-5 for basestation applications that's four times more powerful than the initial version. Expected in the fourth quarter, the SP-20 will clock around 1 GHz. It will be implemented in a 0.13-µm CMOS process. And, it will be backward code-compatible to SP-5 and SP-3 DSP cores.

For details, visit www.3dsp com and www.national.com.

TAGS: Digital ICs
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