Optimized for the APEX 20k family of programmable logic devices (PLDs), the ARC configurable processor core allows designers to quickly and easily customize the 32-bit RISC microprocessor to their specific applications. When executed in the APEX 20k PLD, the user-configured ARC processor can be integrated into system-on-chip designs to optimize performance and cost. Also available is the Xtensa microprocessor core for APEX devices. Available through the web-based Xtensa Processor Generator, the core is able to execute multiple design iterations without charge, making area, speed, power and code density design tradeoffs based on real-time feedback from the generator. When optimal configuration is determined, the designer is able to license and download the APEX-tailored netlist that is then ported to the Altera design environment and implemented on an embedded PLD.
Company: ALTERA CORP.
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