Designer Decisions: Selecting Timing Circuits For Modern Communications

Modern timing architectures used in next-generation networking and wireless infrastructure applications have become increasingly complex. Some of the reasons for the shift include the need to support a broader range of end applications or meet global standards with a single device. A big opportunity for IC vendors is to address the need for integrated CMOS solutions aimed at next-generation networking equipment.  Some analysts put the market opportunity at $1.5 billion in the next few years.

A novel architecture called DSPLL technology can be used to meet the demand of today’s customers. This technology can be employed to create user-programmable XOs and VCXOs that provide any-rate frequency synthesis at jitter levels of 0.3 ps RMS. This phase-locked loop (PLL) technology uses digital signal processing (DSP) techniques to move traditionally analog PLL functions into the digital domain to create a low phase noise, frequency-flexible clock source. The Si570 any-rate programmable XO and the Si571 any-rate programmable VCXO generate any frequency from 10 MHz to 1.4 GHz and target low jitter applications requiring reconfigurable clock sources. The Si57x replaces multiple discrete fixed-frequency oscillators with a single device.

Such any-rate programmable oscillators address the growing need for reconfigurable, low jitter clock sources in next generation networking equipment, telecom infrastructure, wireless base stations, broadcast video, test and measurement and data acquisition.  These products can simplify high-speed clock design, facilitate design reuse, lower system costs and improve reliability in these applications.


DSPLL technology brings capabilities that are not available with traditional surface acoustic wave (SAW) and inverted mesa crystal high frequency fundamental (HFF) oscillator technologies. Using traditional approaches, a unique HFF crystal or SAW resonator must be fabricated for each frequency shipped.  In contrast, Silicon Labs Si57x products use a low-frequency crystal and a DSPLL clock synthesiser IC to generate any output frequency from 10 MHz to 1.4 GHz.  The Si57x devices are available in three speed grades: 10 MHz to 1.4 GHz, 10 MHz to 810 MHz, and 10 MHz to 215 MHz. It is important to provide a user-programmable XO/VCXO that supports any-rate frequency synthesis via a standard I2C interface (Fig.1).


Due to the limited frequency flexibility of traditional XO/VCXO/VCSOs, customers have to manage and maintain a long list of part numbers in their supplier database and hold inventory on long lead item oscillators.  Given the frequency flexibility of the DSPLL IC, the Si57x can potentially replace many fixed-frequency oscillators in a supplier’s database.  This significantly lowers supply chain costs and reduces vendor count.

XO and VCXO customers must be able to select custom frequencies easily with short lead times. By selecting an XO or VCXO that provides any-rate frequency syntheses, a customer can greatly simplify clock circuitry in a wide variety of applications and provide multiple benefits (Fig. 2). The Si57x programmable oscillators can generate any output frequency from 10 MHz to 945 MHz and select frequencies to 1.4 GHz.


In addition, designers can switch between frequencies in a phase continuous or glitchless fashion.  By changing DSPLL divider values via the I2C interface, the output frequency can be changed by as much as ±3500 ppm and the Si57x will produce a continuous output.  Hardware designers can take advantage of this feature in applications that require a range of frequencies be generated by an “always-on” clock source.


An any-rate programmable oscillator can be easily reconfigured to operate at different frequencies, enabling one device to replace multiple fixed-frequency XO/VCXO/VCSOs (Fig. 3).  Increasingly, applications require multiple frequencies to support different high-speed line rates.  Examples of multi-rate applications include 10 G line cards in networking equipment, which must support SONET OC-192, 10 G Ethernet, 10G Fibre Channel, FEC, and proprietary rates; test & measurement, which must support a wide range of rates and HDTV broadcast video (HD-SDI), which must support both U.S. and international transmission rates in the same hardware design.  Designers currently use multiple fixed-frequency oscillators to implement this today.  Because the DSPLL supports any-rate frequency synthesis, one Si57x can replace multiple discrete oscillators while greatly minimising BOM, system costs and board space.


DSPLL technology enables Silicon Labs to generate any frequency using the DSPLL-based Si57x.  Since multiple fixed-frequency oscillators can be replaced with the Si57x, a significant savings in board space and system costs can be realised.

Additionally, an XO or VCXO that can be reprogrammed an unlimited number of times, further simplifies design.  By comparison, fixed frequency oscillators only support a fixed set of frequency plans.  If a different frequency plan is required for a new design, customers have to order a new oscillator, which can take 8-14 weeks for custom frequencies.

Hardware designers can take advantage of the customisable startup frequency feature to provide an initial frequency at board power-up and then change the frequency via the I2C interface to meet each application’s requirements.  Because each Si57x can have a custom I2C address, hardware designers can add Si57x devices to their existing I2C bus without impacting their current design.


An any-rate programmable oscillator should provide excellent jitter performance. Outstanding jitter performance provides additional jitter design margin for hardware designers, making it easier for them to meet system-level jitter requirements.  This becomes important in a number of applications in the high-end market where IC timing performance directly relates to the performance of the end device.

The timing circuitry in modern communications systems is increasingly complex and typically requires a combination of oscillators and clocks.

TAGS: Digital ICs
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