Digital ICs/DSP: Enhanced Host Bridge Chip Adds Features While Lowering Power

Aug. 18, 2005

An upgraded version of the Tsi108 PowerPC host bridge chip, the Tsi108A, adds integrated spread-spectrum clock generation to lower radiated noise and DDR2 memory support for high-speed data transfers. The Tsi108A also has a low active power, typically about 2.5 W with all ports active, and it operates at 200 MHz (3.7 W, maximum). Able to support dual CPUs, PCI-X interfaces, DDR2-400 SDRAM memory, dual Gigabit Ethernet ports, and flash memory interfaces, the chip's additional integrated features lower overall system costs. A low-latency, nonblocking internal switch fabric provides port-to-port interconnects and high throughput. Integrated bus arbiters are available for processors and PCI-X devices. Four independent DMA/XOR channels provide high-speed data-streaming support. The Tsi108A is housed in a 1023-contact, 33- by 33-mm FCBGA. Samples will be available in September. Contact the company for projected pricing.

Tundra Semiconductor Corp.www.tundra.com

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.