Digital ICs/DSP: Mix And Match ASIC Libraries With This Matrix Scheme

March 15, 2004

The Matrix initiative, an ASIC library licensing and integration approach, lets customers use multiple libraries in a single ASIC design to achieve an optimal mix of performance characteristics. Customers can then use the best library for each sub-block in the ASIC by selecting among libraries that have different cell heights, transistor voltage thresholds, and architectures. The scheme also mixes standard-cell and gate-array architectures on the same chip, so the company can minimize the nonrecurring engineering costs associated with crafting derivative versions of an ASIC. The program's first step includes a licensing deal with Virage Logic Corp. to port the Virage libraries to the company's processes and tools.

Kawasaki Microelectronicswww.k-micro.com; (408) 570-0555

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.