Digital ICs/DSP: Registered DDR SDRAM Module Packs 1 Gbit In Small Surroundings

April 12, 2004

Organized as 16 Mwords by 72 bits, a novel registered double-data-rate (DDR) SDRAM module comes in speed grades of 200, 225, or 250 MHz. The W3E16M72SR-XBM multichip solution comes in a 32- by 25-mm, 219-contact plastic ball grid array. In the same footprint, the company will offer a 32-Mword by 72-bit version. Both feature bidirectional data strobes (DQS) transmitted per byte; DQS edge-aligned with data for Reads, and center-aligned with data for Writes. Internally, the memory module uses a pipelined DDR architecture with two data accesses per clock cycle and four internal banks for concurrent operation. In lots of 1000, the multichip module costs less than $200 each. Production lead time is six to eight weeks.

White Electronic Designs Corp.www.whiteedc.com (602) 437-1520

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.