Area- and power-efficient design is the strength behind a new family of PCI-Express physical layers (PHYs). The PHYs come in all lane configurations, including x1, x2, x4, x8, x12, x16, and x32, suiting implementation on TSMC's 130-nm process. They offer a two-tiered approach toward the highly scalable PCI-Express interface technology. The first is a true x1 lane configuration that minimizes area and power to achieve the most efficient design possible. For multilane configurations, the family uses its x4 lane design as a building block for wider designs. The x4 core employs the company's proprietary silicon-proven TriDL (Digital Dynamic Deskewing Logic) architecture to attain highly reliable data-transmission across the link. The PHYs are PIPE 1.0a-compliant hard macros, and they include the serializer/deserializer, the PIPE logic, and the I/Os.