Electronic Design

DSP Brings Felxibility To Wireless Infrastructure

To bring a new level of flexibility to 3G wireless infrastructure equipment while cutting system costs, Analog Devices has unwrapped a derivative of its TigerSharc DSP architecture. The ADSP-TS101S provides both the processing and I/O throughput necessary for the chip-rate and symbol-rate tasks that are required to handle voice and data channels, respectively.

To accomplish these goals without resorting to FPGAs or ASICs, the ADSP-TS101S implements chip-rate and symbol-rate optimized instructions. Plus, it's bundled with layer-1 software for performing the physical-layer algorithms of 3G communications.

"By supporting both chip- and symbol-rate processing tasks as well as physical-layer processing on a single DSP architecture, the ADSP-TS101S delivers an unparalleled combination of performance, flexibility, and lower cost to 3G infrastructure systems," says Andy McCann, ADI's marketing manager for infrastructure DSPs. "It allows for quick migration between major 3G modes that will be deployed in different countries."

Traditionally, node B basestations partition chip-rate and symbol-rate processing between hardware and software, leading to poor resource utilization. As a result, it requires fast, expensive external memory, thereby adding to system cost. Unlike other alternatives, TigerSharc's large internal memory doesn't require external memory.

The ADSP-TS101S provides 6 Mbits of on-chip SRAM, 14 DMA channels, two computational blocks, a sequencer, a cluster bus for interprocessor communications, four link ports, and clocks at 180 MHz. Implemented in 0.13-µm CMOS, it comes in a plastic BGA. It dissipates less than 1 W at 180 MHz.

Sampling now, the ADSP-TS101S is slated for production in the first quarter of 2002. It costs less than $100 in 25,000-unit quantities.

Analog Devices, Three Technology Way, Norwood, MA 02062-9106; (800) 262-5643; www.analog.com.

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