DSP Core Executes One GFLOPS At 100 MHz

Claiming the title of the industry’s first complex domain, extended precision VLIW DSP core, the mAgic delivers up to one GFLOPS at 100 MHz and provides single-cycle execution of complex arithmetic operations, including FFT butterflies and vector2 arithmetic. The core exhibits 40-bit precision with a 32-bit mantissa and an 8-bit exponent field. Its 100-MHz clock rate is said to reduce the need for pipelining, resulting in a higher throughput than faster DSPs. In terms of being a true complex domain architecture, the core is a 128-bit instruction word DSP that simultaneously executes both real and imaginary operations. It includes ten floating- and fixed-point operators, four multipliers, three adders, and three subtractors, arranged in two parallel blocks. Data memory is configured as 512 40-bit registers in two banks of 256 registers, and an additional 80 KB of internal dual-port data memory consists of two sets of three 2k x 40-bit pages. The 8k x 128-bit single-port program memory stores approximately 24,000 instruction cycles of compressed code. The core comes with a visual, modular application development environment (MADE) that includes a macro-assembler/optimizer, GNU compilers, eCos RTOS, and a unified debugging environment. For more details and price, contact ATMEL CORP., San Jose, CA. (408) 441-0311.