DSP Core Eyes Cost Sensitive Apps

Boasting of a price/performance benchmark for low-end SoC/ASIC applications, the company's APE2 very long instruction word (VLIW) DSP core requires as few as 7,000 gates for a 16-bit implementation. Users can configure and customize the core's processing architecture with a parallel structure featuring dynamic data-path routing. Processors can be configured to perform 10 parallel operations per cycle, delivering 1 BOPS throughput at a 100 MHz clock rate. Other features include processing modules such as single cycle MACs and ALUs connected to a common data routing bus. The DSP is configured by choosing the processing module functions and quantities from the library and configuring the width of the data bus in increments as small as a bit at a time. The data bus allows the output of any processing module to be made available at the input of any other and lets the data-path connection or connections change from instruction to instruction. A tool suite is included with licenses, supporting hardware, code, and graphical simulation. The tools automatically generate Verilog source code including any decompression hardware. For further information, contact Patrick Pordage at CAMBRIDGE CONSULTANTS LTD., Cambridge, UK. +44 (0)1223 420024.