EE Product News

DSP Utilizes Quad-Core Design To Deliver 4,800 MMACS

Integrating four 300-MHz SC140 extended StarCore cores and 11.5 Mb of on-chip memory, the new MSC8102 DSP delivers 4,800 MMACS (million multiply accumulates per second) of performance. It also contains a sophisticated multi-level memory hierarchy, high-speed serial communication interfaces, a flexible system interface unit, and a 32-channel DMA engine. This DMA engine enables transfer of data to and from the core L1 and L2 memory and serial interfaces. The chip also includes dual external industry-standard PowerPC (60x-compatible) buses with 9.6-Gbps peak bus throughput.
The MSC8102 is targeted at computation-intense infrastructure DSP applications including packet telephony media gateways, multi-channel modem banks, DSLAMs, and 3G wireless systems. The device is said to be an ideal fit for systems supporting the true convergence of circuit switched voice, fax, modem, and packet-based protocols.
The MSC8102 will be manufactured utilizing 0.13 micron copper interconnect process technology with an estimated power dissipation of 1.6W (300 MHz), all in an 18 mm x 18 mm or 16 mm x 16 mm flip-chip plastic ball grid array (FC-PBGA) package.
Since the MSC8102 is based on the same extended core as the company's MSC8101, developers can take advantage of currently available development tools and real-time operating systems from Metrowerks and third-party suppliers. In addition, the company is working with third-party vendors to provide integrated systems solutions that include GSM, CDMA, TDMA, and ITU G.7xx speech coders, hybrid echo cancellation, fax, modem, and xDSL software.
Pricing of the MSC8102 is estimated to be $181 each/10,000.


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TAGS: Digital ICs
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