Electronic Design

An Easier Path To RTL For DSP Algorithms

Why are so many designers turning to FPGA implementation for DSP designs? Considering the price/performance ratio for today's high-end FPGAs, not to mention the large numbers of DSP blocks and multipliers already included on these devices, it's a no-brainer. Implementing DSP functions in hardware can mean big boosts in performance compared with standard DSP processors, fueling lots of growth.

Most DSP gurus prefer to design at the algorithmic level, generally using tools like MathWorks' Simulink as a high-level schematic-capture tool and simulation environment. Moreover, those DSP gurus aren't apt to be very handy at coding DSP functions in RTL. Thus, they often must hand off the RTL implementation to someone else, launching a time-consuming and error-prone series of iterations.

The real issue is that there's no convenient way to translate the models used internally by Simulink for simulation into RTL. DSP gurus working at the algorithmic level have little or no insight into the implications of choosing one path to RTL implementation versus another. So, they fly blind as they hand off to an RTL coder.

Synplicity steps into this breach with its Synplify DSP software, which takes designs specified at the algorithmic level and automatically converts them into synthesis-ready RTL. Using system-level optimizations, Synplicity says, the tool produces circuits up to 50% faster and 30% smaller than those created using alternative tools. And although Synplicity primarily targets FPGA implementation through use of its Synplify Pro synthesis tool, the RTL that Synplify DSP generates is just as usable on an ASIC as on an FPGA.

Synplify DSP creates a single representation for floating-point and fixed-point modeling of DSP algorithms. The design is implemented from a fixed-point model that has been verified in the MathWorks' Simulink environment, a favored tool for DSP designers. This effectively removes the ambiguity that can result from manual RTL writing.

Synplify DSP optimizes Simulink-based DSP designs at the system level before RTL generation, using algorithms such as system-level retiming. It also inserts pipelining where appropriate. Automatic multichannelization addresses the problems associated with deciding the optimum number of channels for a given design. Users can perform quick "what-if" analyses on thread capacity by automatically generating a multichannel system from a single-channel specification.

The software's "folding" algorithm enables users to perform rapid tradeoffs between performance and area. DSP algorithms can chew up loads of costly hardware functions, such as multipliers. Synplify DSP compensates for this by automatically sharing such hardware resources to fit the design within a performance budget. Analysis of performance/area tradeoffs is done prior to the implementation process, saving iterations as well as silicon area.

Not only does the tool produce RTL code for a given DSP design, it also creates a testbench. The generated RTL model can be verified using any HDL simulator that uses the stimulus from the Simulink environment.

Included in Synplify DSP is a set of functional blocks commonly found in DSP design, such as filtering, transforms, math functions, CORDIC, signal operations, memories, and control logic. The tool also uses FPGA vendors' DSP blocksets as well as the Simulink fixed-point blockset.

Synplify DSP is priced at $39,000 for a perpetual license. Beta software is available now, with a production release scheduled for June.

Synplicity Inc.
(408) 215-6000

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TAGS: Digital ICs
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