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EDA Tool Lets Users Explore Multiple Hardware Architectures

With version 2.2 of A|RT Designer SystemC and ANSI C synthesis tool, designers can interactively and quickly explore multiple hardware architectures to achieve the optimum implementation of complex DSP algorithms prior to going to an HDL. The tool lets designers create libraries of special datapath resources that can execute multiple instructions, such as an FFT butterfly, in a single clock cycle.
A variety of analysis tools, including a graphical view of all datapath resources and a load view that graphically illustrates which resources are being used during each clock cycle, help designers to identify and remove bottlenecks. Users can optimize their designs for power consumption, performance, or silicon.
The software is well suited for the design of ASICs and high-density FPGA system-on-a-chip devices for use in ultra high performance, low-power DSP applications, such as MPEG4, turbo codecs and IMT-2000 for W-CDMA. Prices for the tool start at $45,000.


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TAGS: Digital ICs
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