Electronic Design

Formal Verification Expands To Full Systems-On-A-Chip

A crucial step in design flow is to ensure that the gate-level design representation of an ASIC or system-on-a-chip (SoC) matches the RTL description through formal equivalence checking. Traditionally, though, equivalence checkers force designers to treat much of their SoC as a black box. Memories, complex I/O pads, custom logic, and advanced datapath logic were often rendered opaque to formal verification, leaving some of the design's dicier sections unverified.

Verplex's Conformal 4.0 equivalence checker vanquishes these limitations, making possible full-chip verification for complex designs such as graphics, multimedia, DSP, and communications SoCs. Conformal 4.0 operates independently of implementation tools, eschewing "side files" clandestinely passed from those tools to an equivalence checker. As a result, the risk that formal verification will make the same assumptions that were made in the physical implementation process lessens.

Conformal 4.0 comprises five tools: Conformal LEC, Conformal Datapath (DP), Conformal Logic Transistor Extractor (LTX), Conformal Memory, and Conformal Layout Versus RTL (LVR). All operate within the same user interface and share similar debugging approaches.

Conformal LEC provides Verilog 2001 support, hierarchical comparison, design mapping, and a schematic viewer. Users also benefit from up to 10× performance improvements for gate-to-gate comparisons and up to 5× for RTL-to-gate comparisons. A three-year, time-based license starts at $57,600. Conformal DP users can automatically verify flat datapath modules, complex merged operators, advanced pipelining techniques, and carrysave architectures.

See associated figure

Verplex Systems Inc.

TAGS: Digital ICs
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