Most analysts agree that this year, the growth rates of field-programmable gate arrays (FPGAs) will actually double that of application-specific integrated circuits (ASICs). Of course, FPGAs have been gaining market traction for some time. Seeing their potential, a number of companies have worked to provide more of an FPGA-centric offering. An example is AccelChip, which offers tools to improve the design-flow productivity of FPGAs.
This startup company develops top-down DSP synthesis tools. Recently, AccelChip made news with enhancements to its AccelFPGA program. This tool was introduced last year. The latest version automatically generates synthesizable register-transfer-level (RTL) Verilog and VHDL models with testbenches directly from MATLAB and Simulink designs. These models and testbenches can be used in most major FPGAs. The company claims that AccelFPGA is the only EDA tool that can synthesize MATLAB—a widely used tool for DSP development.
The ability to go from MATLAB designs to customizable silicon, such as FPGAs, is critical. There is a growing need to implement DSP algorithms in hardware. Today's cellular and wireless data networks require high-performance DSPs. One way to meet these needs is to transition the implementation of DSP algorithms from software to hardware. FPGAs can provide a low-cost alternative to ASICs for many of these algorithmic implementations. Unfortunately, the traditional DSP-FPGA design flow requires designers to manually create RTL models and simulation testbenches from the DSP design. This process can be time consuming—taking up to six man months. It also can be very error prone.
In contrast, AccelChip allows developers to automatically evaluate and then directly implement algorithms in silicon. It promises to reduce the standard hardware design cycle, thanks to the time savings gained in many tasks. For example, DSP developers no longer need to write hardware specifications for FPGA implementations. They don't have to manually create RTL models either. Verification engineers also benefit. They are freed from having to simulate these RTL models for equivalence with the MATLAB source models.
Clearly, the enhancements in Accel-FPGA 2.0 are aimed at making FPGA implementations as easy as possible for traditional DSP designers. For example, version 2.0 features improved MATLAB language coverage, including support for hierarchical MATLAB files (M-files). These files enable the use of customer scripts without restructuring the design.
Another key improvement is the automated conversion of MATLAB models from floating-point to fixed-point representations. Typically, DSP designers use floating-point modeling in all of their design elements. They can then develop the best algorithm for a given application without worrying about the limited precision effects of actual implementation.
With a new process-oriented graphical user interface (GUI), AccelChip 2.0 hopes to enhance the tool's usability. This GUI allows the user to move from M-files to architecture-specific FPGA implementations in one environment (see figure). AccelFPGA 2.0 supports Xilinx and Altera FPGAs as well as Elixent's D-Fabrix embedded reconfigurable arrays.
For DSP designers, the tool's greatest benefit may be that it gives them the ability to quickly explore design tradeoffs. In AccelFPGA 2.0, a structural view of hierarchical M-files is automatically created at the outline level. This view helps DSP designers analyze key dependencies. After analyzing the structures and dependencies of the MATLAB files, AccelFPGA 2.0 diagrams the design's hierarchy. It also identifies inputs and outputs. DSP designers can then browse the hierarchy, view the M-files, and verify the completeness of the design. More importantly, they can explore different FPGA implementations for speed and area tradeoffs.
Once the design tradeoffs are evaluated, a RTL can be synthesized from MATLAB. But how can the designer ensure that FPGA implementation provides an accurate cycle-by-cycle representation of the DSP design? For AccelFPGA, the answer is to automatically create a simulation testbench. This testbench exercises the gate-level FPGA design using vectors from the original MATLAB simulation. The burdensome task of manually coding and recoding the simulation testbench is thereby eliminated.
The automatic importation of foreign models also is provided in AccelFPGA 2.0. It is a precursor for a new library of DSP intellectual property (IP) dubbed AccelWare. This IP library is slated for release later this year. AccelFPGA 2.0 is available now. It is priced from $25,000.
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